FPGA Up Cast Funktion deletes Values form Read/Write Controll

Hello Everybody,
I Have an other Problem with my RT-FPGA cRIO...
I have now managed to read the module IDs to convert this combination in a certain casenumber and this one then selects the FPGA File. Now is that I have inbounded various FPGA Bitfiles. If I composed them by the the "Up Cast function" to a universal reference then there will disappear some elements by using the Read / Write Control .
I have a picture attached that this Clarifies!
The first two R / W Controller have been up before the cast and the third upcast diverted after.
I hope you can help me!
thank you in advance before
MaJahn

Even now I've noticed the function Invoce methode: Read TEDS is also no longer supported.
Why?!
The both VIs are exactly the same during the Modules in it are different.
Iam using LabVIEW 2009 and the newest Drivers from the NI site!

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Incorrect data type when writing to FPGA Read/Write Control

I have run in to a problem this morning that is causing me substantial headache. I am programming a CompactRIO chassis running in FPGA mode (not using the scan engine) with LabVIEW 2012. I am using the FPGA Read/Write Control function to pass data from the RT Host to the FPGA Target. The data the RT host is sending comes from a Windows host machine (acting as the UI) and is received by the RT Host through a network published variable.
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The problem comes in the RT code. After I read the shared variable I unbundle the cluster by name, exposing the sub-cluster of fixed point numerics. I then drop an FPGA Read/Write Control on the RT block diagram and wire up the FPGA reference. I left click on the FPGA Read/Write Control and select the cluster of fixed point numerics. I wire these together and get a coercion dot. Being a coercion dot hater, I hover over it the dot and see that the wire data type is correct (type def cluster of fixed point numerics), but the terminal data type is listed as a cluster containing a Boolean, code integer and source string, also known as an error cluster. I delete the wire and check the terminal data type on the Read/Write Control, which is now correctly listed as a type def cluster of fixed point numerics. Rewiring it causes the terminal to revert back to the error cluster. I delete the wire again and right click on the terminal to add a control. Sure enough, a type def cluster of fixed point numerics appears. Right clicking and adding an indicator to the unbundle attached to the network shared variable produces the proper result. So, until they are attached to each other, everything works fine. When I wire these two nodes together, one spontaneously changes to a error cluster.
Any thoughts would be appreciated.

My apologies I never got back to responding on this. I regret that now because I got it to work but never posted how. I ran in to the exact same problem today and returned to this post to read the fix. It wasn't there, so I had to go through it all over again.
The manifestation of the problem this time was that I was now reading from the Read/Write FPGA front panel control and writing to a network published shared variable. Both of these (the published shared variable and the front panel control) were based on a strict type defined cluster, just like in the original post. In this instance, it was a completely different cluster in a completely different project, so it was not a one-off thing.
In addition to getting the coercion dot (one instance becoming an error cluster, recall), LabVIEW would completely explode this time around. If I saved the VI after changing type definition (I was adding to the cluster) I would get the following error:
Compile error. Report this problem to N.I. Tech Support. Copy cvt,csrc=0xFF
LabVIEW would then crash hard and shutdown without completing the save. FYI, I'm running LabVIEW 12.0f3 32-bit.
If I would then reopen the RT code, the same crash would occur immediately, ad nauseam. The only way to get the RT code to open was to change the type defined cluster back to the way it was (prior to adding the new element).
I didn't realize it last time around (what originally prompted this post), but I believe I was adding to a type def cluster when this occurred the first time.
So, how did I fix it this time around? By this point I tried many, many different things, so it is possible that something else fixed it. However, I believe that all I had to do was to build the FPGA code that the RT code was referencing. I didn't even have to deploy it or run it... I just had to build it. My guess is that the problem was the FPGA Reference vi (needed to communicate with the FPGA) is configured (in my case) to reference a bit file. When the development FPGA Main.vi ceases to match the bit file, I think that bad things happen. LabVIEW seems to get confused because the FPGA Main.vi development code is up and shows the new changes (and hence has the updated type def), but when you ask the RT code to do something substantial (Open, Save, etc), it refers to the old bit file that has not yet been updated. That is probably why the error getting thrown was a compile error.
I'm going to have to do an additional round of changes, so I will test this theory. Hopefully I will remember to update this post with either a confirmation or a retraction.

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Hi Akiel,
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FPGA Read/Write Control Issues

Hello all! Rather new to using FPGA, but I have an interesting issue that's popping up.
Currently pulling in RAW voltage data from a set of sensors (Pressure Transducers, Load Cells, etc) through a cRIO DAQ. Have the FPGA file setup to pull in that data already and have the main VI and all the sub-VIs working just fine.
What I'm trying to do is save the raw voltage data (TDMS files) on the lower level and the convert and display on the upper level so that I don't have to convert and save (speed up saving data). So that leaves 3 distinct levels/sections:
On FPGA that pulls in the raw data
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Hi,
HySoR wrote:
The issue I'm having is when I use the FPGA Read/Write control to read in from the Target and save to the TDMS. When I only use a single FPGA target reference the lines are broken, but as soon as I switch to two targets, it now works.
Could you take a screenshot and post this part of your code? I'm having trouble understanding what you are describing.
Craig H. | CLA | Systems Engineer | National Instruments

FPGA Read/Write Control Function Issues

Hello all! Rather new to using FPGA, but I have an interesting issue that's popping up.
Currently pulling in RAW voltage data from a set of sensors (Pressure Transducers, Load Cells, etc) through a cRIO DAQ. Have the FPGA file setup to pull in that data already and have the main VI and all the sub-VIs working just fine.
What I'm trying to do is save the raw voltage data (TDMS files) on the lower level and the convert and display on the upper level so that I don't have to convert and save (speed up saving data). So that leaves 3 distinct "levels/sections":
On FPGA that pulls in the raw data
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Number two is where I'm having an issue. I want to save all the data in parallel so I'm creating a save FPGA for the I/O devices (8 Relays to command solenoid valves, 3 Pressure Transducers, 1 Load Cell, 4 Thermocouples).
The issue I'm having is when I use the FPGA Read/Write control to read in from the Target and save to the TDMS. When I only use a single FPGA target reference the lines are broken, but as soon as I switch to two targets, it now works.
I've attached a screen cap of the current problem. The set-up on the bottom (with only one target) doesn't work. But the second I add more than one target, it works.
Any reason why it might be doing this? Any ideas/suggestions at all on how to go about setting this up in general?
Thanks!
Attachments:
FPGAError.jpg ‏35 KB

HySoR,
You might check the documentation for "data" terminal of "TDMS Write" (http://zone.ni.com/reference/en-XX/help/371361H-01/glang/tdms_file_write/). One DBL element is not accepted, but 1D DBL array is accepted.
data is the data to write to the.tdmsfile. This input accepts the following data types:
Analog waveform or a 1D array of analog waveforms
Digital waveform
Digital table
Dynamic data
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Signed or unsigned integers
Floating-point numbers
Timestamps
Booleans
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FPGA Coercion Context Help.png ‏36 KB

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I'm playing with a 5644 VST and the VST Streaming template. On the FPGA VI I added some code, then added an indicator to the FPGA VI front panel and compiled. Running the FPGA VI in interactive execution mode, the indicator works well. On the host end, though, I can't seem to access the new indicator with a Read/Write control.
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GlennA wrote:
Hi
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FPGA Up Cast Funktion deletes Values form Read/Write Controll

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