Imaqio (fpga) PCIe 8255R read/write control ISO input

Hi. I have an external trigger connected to ISO INPUT 5 on my PCIe 8255R which has an fpga RIO (see manual). I want to read the value of ISO INPUT 5 using Read/Write control vi on Labview but this vi doesn't show that input (it shows iso inputs from 6 to 11). I'm using the default IMAQIO bitfile that comes in the installation directory to open the FPGA. What should I do?. Thanks in advance.

Hi Akiel,
Thanks for your question, I'm guessing the reasoning behind this is that you have a large number of indicators?
Whilst there isn't an in-built way of dynamically referencing which indicator on the FPGA to read from, there is a custom FPGA interface tool which may be of some use to you:
https://decibel.ni.com/content/docs/DOC-17185
If you read through this, let me know if this helps or if you need any help understanding what this is doing.
Regards,
Ben Clark

Similar Messages

Incorrect data type when writing to FPGA Read/Write Control

I have run in to a problem this morning that is causing me substantial headache. I am programming a CompactRIO chassis running in FPGA mode (not using the scan engine) with LabVIEW 2012. I am using the FPGA Read/Write Control function to pass data from the RT Host to the FPGA Target. The data the RT host is sending comes from a Windows host machine (acting as the UI) and is received by the RT Host through a network published variable.
The network published shared variable (shared between the RT and Windows system) is a Type Def cluster containing several elements, one of which is a Type Def cluster of fixed point numerics. The RT system reads this shared variable and breaks out the individual elements to pass along to various controls on the FPGA code's front panel. The FPGA's front panel contains a type def cluster (the same type def cluster, actually) of fixed point numerics.
The problem comes in the RT code. After I read the shared variable I unbundle the cluster by name, exposing the sub-cluster of fixed point numerics. I then drop an FPGA Read/Write Control on the RT block diagram and wire up the FPGA reference. I left click on the FPGA Read/Write Control and select the cluster of fixed point numerics. I wire these together and get a coercion dot. Being a coercion dot hater, I hover over it the dot and see that the wire data type is correct (type def cluster of fixed point numerics), but the terminal data type is listed as a cluster containing a Boolean, code integer and source string, also known as an error cluster. I delete the wire and check the terminal data type on the Read/Write Control, which is now correctly listed as a type def cluster of fixed point numerics. Rewiring it causes the terminal to revert back to the error cluster. I delete the wire again and right click on the terminal to add a control. Sure enough, a type def cluster of fixed point numerics appears. Right clicking and adding an indicator to the unbundle attached to the network shared variable produces the proper result. So, until they are attached to each other, everything works fine. When I wire these two nodes together, one spontaneously changes to a error cluster.
Any thoughts would be appreciated.

My apologies I never got back to responding on this. I regret that now because I got it to work but never posted how. I ran in to the exact same problem today and returned to this post to read the fix. It wasn't there, so I had to go through it all over again.
The manifestation of the problem this time was that I was now reading from the Read/Write FPGA front panel control and writing to a network published shared variable. Both of these (the published shared variable and the front panel control) were based on a strict type defined cluster, just like in the original post. In this instance, it was a completely different cluster in a completely different project, so it was not a one-off thing.
In addition to getting the coercion dot (one instance becoming an error cluster, recall), LabVIEW would completely explode this time around. If I saved the VI after changing type definition (I was adding to the cluster) I would get the following error:
Compile error. Report this problem to N.I. Tech Support. Copy cvt,csrc=0xFF
LabVIEW would then crash hard and shutdown without completing the save. FYI, I'm running LabVIEW 12.0f3 32-bit.
If I would then reopen the RT code, the same crash would occur immediately, ad nauseam. The only way to get the RT code to open was to change the type defined cluster back to the way it was (prior to adding the new element).
I didn't realize it last time around (what originally prompted this post), but I believe I was adding to a type def cluster when this occurred the first time.
So, how did I fix it this time around? By this point I tried many, many different things, so it is possible that something else fixed it. However, I believe that all I had to do was to build the FPGA code that the RT code was referencing. I didn't even have to deploy it or run it... I just had to build it. My guess is that the problem was the FPGA Reference vi (needed to communicate with the FPGA) is configured (in my case) to reference a bit file. When the development FPGA Main.vi ceases to match the bit file, I think that bad things happen. LabVIEW seems to get confused because the FPGA Main.vi development code is up and shows the new changes (and hence has the updated type def), but when you ask the RT code to do something substantial (Open, Save, etc), it refers to the old bit file that has not yet been updated. That is probably why the error getting thrown was a compile error.
I'm going to have to do an additional round of changes, so I will test this theory. Hopefully I will remember to update this post with either a confirmation or a retraction.

FPGA Read/Write Control Issues

Hello all! Rather new to using FPGA, but I have an interesting issue that's popping up.
Currently pulling in RAW voltage data from a set of sensors (Pressure Transducers, Load Cells, etc) through a cRIO DAQ. Have the FPGA file setup to pull in that data already and have the main VI and all the sub-VIs working just fine.
What I'm trying to do is save the raw voltage data (TDMS files) on the lower level and the convert and display on the upper level so that I don't have to convert and save (speed up saving data). So that leaves 3 distinct levels/sections:
On FPGA that pulls in the raw data
On FPGA that saves the raw data
Main VI that does all the controls/conversions/displays etc.
Number two is where I'm having an issue. I want to save all the data in parallel so I'm creating a save FPGA for each I/O device (8 Relays to command solenoid valves, 3 Pressure Transducers, 1 Load Cell, 4 Thermocouples). To do this I want to create a separate VI for each device (not sure if that's a smart thing to do).
The issue I'm having is when I use the FPGA Read/Write control to read in from the Target and save to the TDMS. When I only use a single FPGA target reference the lines are broken, but as soon as I switch to two targets, it now works.
Any reason why it might be doing this? Any ideas/suggestions at all on how to go about setting this up in general?
Thanks!

Hi,
HySoR wrote:
The issue I'm having is when I use the FPGA Read/Write control to read in from the Target and save to the TDMS. When I only use a single FPGA target reference the lines are broken, but as soon as I switch to two targets, it now works.
Could you take a screenshot and post this part of your code? I'm having trouble understanding what you are describing.
Craig H. | CLA | Systems Engineer | National Instruments

FPGA Up Cast Funktion deletes Values form Read/Write Controll

Hello Everybody,
I Have an other Problem with my RT-FPGA cRIO...
I have now managed to read the module IDs to convert this combination in a certain casenumber and this one then selects the FPGA File. Now is that I have inbounded various FPGA Bitfiles. If I composed them by the the "Up Cast function" to a universal reference then there will disappear some elements by using the Read / Write Control .
I have a picture attached that this Clarifies!
The first two R / W Controller have been up before the cast and the third upcast diverted after.
I hope you can help me!
thank you in advance before
MaJahn

Even now I've noticed the function Invoce methode: Read TEDS is also no longer supported.
Why?!
The both VIs are exactly the same during the Modules in it are different.
Iam using LabVIEW 2009 and the newest Drivers from the NI site!

FPGA Read/Write Control Function Issues

Hello all! Rather new to using FPGA, but I have an interesting issue that's popping up.
Currently pulling in RAW voltage data from a set of sensors (Pressure Transducers, Load Cells, etc) through a cRIO DAQ. Have the FPGA file setup to pull in that data already and have the main VI and all the sub-VIs working just fine.
What I'm trying to do is save the raw voltage data (TDMS files) on the lower level and the convert and display on the upper level so that I don't have to convert and save (speed up saving data). So that leaves 3 distinct "levels/sections":
On FPGA that pulls in the raw data
On FPGA that saves the raw data
Main VI that does all the controls/conversions/displays etc.
Number two is where I'm having an issue. I want to save all the data in parallel so I'm creating a save FPGA for the I/O devices (8 Relays to command solenoid valves, 3 Pressure Transducers, 1 Load Cell, 4 Thermocouples).
The issue I'm having is when I use the FPGA Read/Write control to read in from the Target and save to the TDMS. When I only use a single FPGA target reference the lines are broken, but as soon as I switch to two targets, it now works.
I've attached a screen cap of the current problem. The set-up on the bottom (with only one target) doesn't work. But the second I add more than one target, it works.
Any reason why it might be doing this? Any ideas/suggestions at all on how to go about setting this up in general?
Thanks!
Attachments:
FPGAError.jpg ‏35 KB

HySoR,
You might check the documentation for "data" terminal of "TDMS Write" (http://zone.ni.com/reference/en-XX/help/371361H-01/glang/tdms_file_write/). One DBL element is not accepted, but 1D DBL array is accepted.
data is the data to write to the.tdmsfile. This input accepts the following data types:
Analog waveform or a 1D array of analog waveforms
Digital waveform
Digital table
Dynamic data
1D or 2D array of:
Signed or unsigned integers
Floating-point numbers
Timestamps
Booleans
Alphanumeric strings that do not contain null characters

FPGA Read Write Control Coercion

I am getting a coercion indication using a FPGA read write control. I have attached a screen capture of the context help. For some reason it is looking for an error cluster?
Attachments:
FPGA Coercion Context Help.png ‏36 KB

The NI 9229 Data Rate Control.
See attachments
Attachments:
FPGA Coercion VI.png ‏76 KB
FPGA Coercion VI 2.png ‏129 KB

Shortcuts for change in read/write (control/indicator)

Hello,
I try to find a shortcut for change to read/write a local variable ?
Thanks
Sylvain Jourdan
(Labview 2012 - English)

Hi,
Thanks for you quick answer, I'll suggest this idea in the LabVIEW-IdeaExchange.
An other idea, do you know if we can add a property to the shorcut menu by modifying a configuration file... ?
Thanks,
Sylvain
Attachments:
option_menu.png ‏53 KB

Read write control on status

Dear All,
I have a problem. Look at the senario,
i have a table ATTENDANCE_HEADER in which there is a column STATUS,
there is another table ATTENDANCE_DETAILS.
entry to the ATTENDANCE_HEADER table is automatic by using schedules setting the STATUS column to PLANNED value.
means the current date master entry will be entered inthe HEADER table with PLANNED status.
The secretary will be allowed to do entries in the Details table for PLANNED status.
but when manager change the status of attendance to RELEASED,Secretary and even the manager and anybody
will not be able to change the ATTENDANCE_DETAILS rows which are against a date which is RELEASED in the ATTENDANCE_HEADER.
How should i implement this type of security?
i need a method example if posible.
Thanks & Regards

Muhammad wrote:
third tip was new for me and is nice, although i am not understanding completely the purpose of it,
why Table to relate users with their Roles? what will be the structure of these 3 tables?
Thanks again.its about One to Many or One to Relation thing......
if one user can have multiple Roles then u need this 3rd table....
else u can save the Role reference key in the USER main table
Users
User_id number,
User_name Varchar2
App_roles
App_role_id number,
App_role_name varchar2
Users_roles
User_id number,
App_role_id numberu can create many tables its all depends how u can handle
my 2 cents

Read/Write PCI Memory

Hi All,
This question may be outside the scope of Java and this forum (appologies if so). However, I'm trying to read/write some PCI memory locations in either Linux or Windows. I'd like to access these locations via Java. Is there any direct method to do this? Is there an API to access more low level hardware? Currently, I can read/write the memory locations with a program called PciTree. So, I know my PCI device is working, and the basic driver for the PCI device is installed.
If this is not possible in Java, I can try C and study the device driver's functionality.

You could write something in C/C++ and then expose methods to Java via JNI. But Java doesn't have built-in support for accessing memory at that level. A third party library may be availble though. Good luck.

Read/Write vs Full Control on KM folders/files

I've read some docs on what Read/Write vs Full Control permissions mean when setting permissions for users/groups for folders and files. But I'm still somewhat confused.
What exactly does the 'Write' mean in Read/Write. Does Write mean a user can:
Create a new folder
Create a new file
Modify an existing file
Delete a file
Delete a folder
When you use the pull down for setting permissions, you see: Full Control, Read/Write, Read, Write and Delete. Kind of confusing. And you can only select one of them.
Any clarification on these permissions would be greatly appreciated. Or pointing me to some good documentation.
Thanks in advance. Ron

Access authorizations
Read
Permission to display items.
Write
Permission to change items but not to display them.
In folders, this permission also allows users to create items.
Read/Write
Permission to display and change items.
In folders, this permission also allows users to create items.
Delete
To delete an item, you require delete permission (or full control) for this item and write permission for the superordinate folder.
Full Control
This permission contains all other permissions.

Adobe Acrobat Standard I/O Reads Writes Out of Control

I am using Adobe Acrobat Standard 9.3.2 on Windows XP SP3 with the latest updates installed. In the last few months I have frequently caught acrobat.exe running even when I had no acrobat windows open. The way I know when this is occurring is because my disk read/write light goes crazy. When I open up the task manager I see that Acrobat has hundreds of thousands of disk I/O reads and writes. It is almost like it is caching itself or something. Anyway, does anyone else have this problem and/or know how to make this stop? Right now I just have to go in and force close the app via the Task Manager.
Thanks in advance,
CF

Thanks but I have tried both with and without acrotray running first and it still occurrs. Additionally, when I open it in relation to reboots doesn't matter. The only thing that I think might change behavior is whether or not Acrobat has been opened inside a web browser. There may be some question as to whether or not IE or FF close it properly.

Urgent!!! Need help in file read/write data to a serial port

Hi,
I really need someone's help in order for me to complete my project. I have attached a vi which I have taken from an example and integrate to my project. In the vi, I have managed to get the encoder counts using Ni 9411. I need to read/write that data from ni9411 to ni9870 without using any serial port as they are connected to a NI 9104 chasis. May I know whether I am correct in writing the data to my ni9870 port using the vi I have attached? Does anyone know how i can convert the number of counts to a 8-bit data/byte so that I can send the data through the RS232 port? I really need someone's help as I need to finished in 2 weeks time.
I have also attached an vi on controlling the epos2 controller using instrument driver. Does anyone know how can i integrate this vi to the fpga vi (the one which I need to read/write data to 9870) as I need to send those data to control my epos2 controller.
Please help me!!!
Attachments:
Encoder Position & Velocity (FPGA).vi ‏23 KB
SINGLEMOTORMODIFIED.vi ‏17 KB

Afai,
As I allready suggested you here, call your local NI Office and ask for assistance!
You really need assistence in a higher level that we can provide via the forums. Otherwise I don't see a chance for you to finish your project in time.
1. Convert I32 to U8 to write it to the 9870 could be done like this:
2. The vi to control the epos2.
There is NO way ( absolutely NO way) to port this vi to FPGA. It's based on VISA calls, uses an event-structure, both are not available at the FPGA.
The only thing you could do is to analyze the VI, the instruction set and design an FPGA vi which handles the specific instructions you would need.
I have no experience with epos2 and I'm not 100% sure if this would work as you would like to use it. And doing this needs deep knowledge of LabVIEW, VISA, Instrument Drivers, the epos hardware, FPGA programming, and so on...
Christian

FPGA Digital Channel Read

I am using the PCI-7831R, and the signal is connected to Channel 2.
Using the FPGA I/O Node to read in 12 pins. My question is, is it a serial read or a parallel read?

You define your signals as either a digital line (serial read/write) or a digital port (parallel read/write). This can be seen if you add FPGA I/O to your target. Here's some screenshots of both single and port signals:
Note the "resolver" data is composed of two ports of 8 bits each whereas the BITE ENABLE lines are individual signals. You can tell if you are using digital line or port by the type, lines are shown as booleans, ports are shown as unsigned 8 bit integers.
Message Edited by Bill@NGC on 07-20-2007 06:53 PM
“A child of five could understand this. Send someone to fetch a child of five.”
― Groucho Marx
Attachments:
fpga io3.png ‏3 KB
fpga io.png ‏11 KB
fpga io2.png ‏5 KB

Can I read/write global variables that are in other PC?

I attach the vis and the executables.
My problem is that when I run( continuosly, because in other way, I read the default value of the variable) getvalue.vi and setvalue.vi, I don´t have any problem, I can read/write the global variables, the two vis is running in the same PC.
But when I do the exe and I run them continuosly , it doesn´t work.
Any solution?
Thanks in advanced!
Graci
Attachments:
Get_Value.vi ‏30 KB
Set_Value.vi ‏30 KB
Exe.zip ‏272 KB

Hello Bichillo,
By running the vis continuously you are running into race conditions. If you cannot control when you are writing to or reading from a global variable, you cannot know whether the value writen/read is the right one or not.
In your case the global variable value that is read is sometimes the last value writen and sometimes an empty string.
To make the global variable behave as desired, that is, keeping its last value, the global variable must be in memory when you access it using VI Server. If it is not in memory, the returned value is an empty string. That´s why you sometimes get a non-empty string: when you access the global variable to read its value, it happens to be in memory because you´ve just writen to it.
To ensure that the global
variable is always in memory and it keeps its last value, you must include the global variable into your block diagram. I am attaching modified vis that implement this.
Hope it helps.
César Verdejo
Training and Certification | National Instruments
Attachments:
Get-_Set_Value.llb ‏48 KB

Why doesn't Photoshop support read/write of .mpo files?

I am actually blown away that I cannot find a single Photoshop plugin that reads and/or saves .mpo files. Does somebody know why? And why isn't anyone talking about this format? I find it hard to believe that no one in the entire Photoshop Windows forum has ever wondered about Photoshop's complete lack of or interest in support for .mpo files.
If nobody knows how to read/write .mpo files directly through Photoshop, perhaps someone could point me to some documentation for writing a plugin for it. It's a really really simple file format--there's no reason that a plugin shouldn't be available already.
Thanks in advance for your support.
Jase

Well wave of the future or not. its beening pushed hard. That is in a way good for us the consumers.. choice is always good.
3d tv's and monitors require at least 120hz in order to function. what does that mean for people who spend all their time in front of a monitor?
Bringing about the availablilty of 120hz and beyond flat panels.
Many are people are prone to getting migrains due to refresh rates 60 hz or less, Most people getting migrains from sitting at work in front of a 60 hz monitor all day long, and do not even realize it.
I happen to be one of those people who get migrains, especially if I am doing artwork for 8 - 10 hours.
I just picked up a 120 hz monitor like 2 weeks ago cause I am a techno junky and love my toys, it is the asus one that comes with the Nvidia glasses.
There is nothing wrong with my other monitor, a 24 inch HP monitor. Its a 1920 x 1200 5ms responce time 60hz monitor.
I didn't think i would really even notice the difference between a 120 hz and 60 hz monitor.
Boy ohh boy was I ever mistaken about not Noticing. sitting side by side, to me the picture difference is amaizing. Now i have not had an oppertunity to do a real weekend artwork fest but that will come with time.
The 3d features with the glasses on, I think are very cool in games its extreemly noticable since you have more control over what it is you are looking at. I am not sure i would play a game end to end for hours and hours in 3d. i think that would likely make my head explode but we'll see about that too and if not my be running into walls when i am done since you tend to loose perseption. not to mention 3d glassses make it so you see each picture at 60 hz in one eye 60 hz in the other putting you back to a 60 hz refresh and migrains.
anyway way off subject, but to sum it up.
Some good things can come from flavor of the day fads. Grant it some bad some times does too.. i mean look at bell bottoms....

Imaqio (fpga) PCIe 8255R read/write control ISO input

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