FPGA Virtex 2 pro

Hi,
Is it possible to use LabView FPGA to create a program and then write the created file to a Memec Virtex 2 Pro development board?
I understand it can work with theVirtex 2 Pro chip when it is in the NI RIO but is it possible to use the created firmware with a 3rd party board?
Thanks
Alex

cRIO, sbRIO, myRIO, R series boards: all FPGA boards made by NI!
Best regards,
GerdW
CLAD, using 2009SP1 + LV2011SP1 + LV2014SP1 on WinXP+Win7+cRIO
Kudos are welcome

Similar Messages

Is it possible to run PowerPC which is included in Virtex II pro on NI 5640R radio IF transceiver?

Hi,all.
I am interested to find out how to run this PowerPC by LabVIEW (e.g. LabVIEW Real time module) on this device (NI 5640R). I am not sure is it possible or not at all ... Maybe someone has any experience ?!

I have no exact goal to accomplish. At moment I'm just playing around with this transceiver in LabVIEW FPGA. And AFAIK it is possible to communicate between LabVIEW FPGA and LabVIEW RT VI's ... so in my opinion it should be very interesting to manage any parallel processes performed by FPGA using on same chip included silicon CPU.

Filtre numérique à l'aide d'une équation récurrente dans FPGA

Bonjour à tous,
Je souhaite implémenter un filtre numérique dans un FPGA (Virtex-II à 1 million de portes logiques).
Pour cela j'ai calculer mon équation récurrente qui est : S(n) = (1/b0)*[a0.E(n) + a1.E(n-1) + a2.E(n-2) - b1.S(n-1) - b2.S(n-2).
Je me suis dis qu'implémenter cette équation serait facile avec les registres à décalages mais finalement j'ai plutôt un problème avec le format des datas.
En effet, les coefficients calculés sont très petits. Par exemple a0 = 0,01226993865.
Et donc en utilisant le format FXP (virgule fixe), je dois mettre le format <+/-,39,2> : [-2,000000E+0 , -2,000000E+0]:7,275958E-12 , pour avoir la résolution adéquate à mes coefficients.
Le problème c'est que lors d'une multiplication, le nombre de bits "word length" (39 dans mon exemple) et "integer word length" (2) est doublé...
Avec un maximum de 64bits pour le "word length", j'atteins vite la limite...
Avez-vous une idée pour la mise en oeuvre de ce filtre ?
Une astuce à utiliser pour manipuler des nombres très petits dans un FPGA ?
Benjamin
Résolu !
Accéder à la solution.

Bon, voilà comment j'ai fais :
Depuis mon controleur, je multiplie par 2^15 mes coefficients puis je les envoie dans mon FPGA.
Et dans mon équation récurrente sur FPGA, je multiplie ma sortie par 2^(-15) !
Et le tour est joué !

Remote configuration question

Hello! I have several questions about configuration in my system that is shown on picture.
I need to have a possibility to program the second FPGA(Virtex-6) and its flash memory. I'm going to send mcs or bit file via ethernet to FPGA 1(Kintex-7) then programming in JTAG-mode FPGA 2 or its flash. First of all, i need to develop JTAG configuration logic at FPGA-1. Then, i have a questions:
1) Is it possible to detect in the jtag chain a flash memory of the FPGA 2 and programm it via FPGA-1? Or its only possible to programm it only using Impact and jtag-programmer?
2) I would like to know if my jtag-configuration logic (at FPGA-1) will have mistakes, is it possible to damage fpga-2 by sending wrong sequences of bits during configuration it "on fly"?

XSVF is something like taking a straight-forward iMPACT programming process, and then recording the transitions of the JTAG signals. Then what you do is to "play back" the recording to make the same thing happen within your target system. Pretty much anything you do in iMPACT including indirect flash programming (SPI or BPI) can be converted into XSVF.
You could also roll your own JTAG conversion code, but I think that will take a lot more effort. I would not be too worried about damaging the FPGA, however. Typically errors in the configuration process are detected as CRC errors and prevent the part from running bad codes.

Virtex-7 FPGA VC707

Virtex - 7 FPGA VC707 power module could not be started no what the output would be sent back to the xilinx can help repair

hi,
you need to go through the debug checklist available at http://www.xilinx.com/support/answers/51233.html
this will help determine if the board is functional.
--hs

Connecting 5V digital intputs to Virtex 5 FPGA

Hello,
I would like to connect 5V digital pins of ds1103 dSPACE board to the digital inputs of the Virtex 5 FPGA.
I have read (http://www.xilinx.com/support/answers/10835.html) that the digital input voltages to the FPGA can actually be a bit higher than 3.3V as long as the current does not exceed 10mA. They recommand connecting a resistor in series in order to guarantee that. However, the digital outputs from the dSPACE board (whose voltage can be lower than 5V depending on the load) cannot provide more than 10mA anyway so there should not be any limitation problem.
Still, I am not completely confident about connecting 60 pins of 5V from dSPACE to the FPGA. Can anyone confirm that the direct connection (without the series resistor) will not harm the FPGA? Or is it still preferrable to use series resistors (x60)?
Thank you
Thomas Geury

Thank you for your reply.
The dSPACE board digital pins output an absolute maximum current of 10 mA, so only the latch-up limit is a constraint.
I will indeed consider using series resistors then. If the voltage (max) from the dSPACE pins is 5V, and the clamp diodes of the FPGA I/Os are forward-driven for a voltage of at least 3.5V (see http://www.xilinx.com/support/answers/10835.html), then the resistors guaranteeing a current limited to 100 mA / 60 inputs should be (5-3.5)/(10e-3/60) = 900 ohms, right? Is that how you got to 2,000 ohms, including a safety margin as there will be a few output pins used as well?
Also, is the latch-up limit of 100 mA for the whole FPGA or per bank? I see on the datasheet (see http://www.xilinx.com/support/documentation/data_sheets/ds100.pdf, page 2) that my model (Virtex 5 XC5VLX50) has 17 I/O banks; would that allow me to use I/O of different banks in order to have an overall higher latch-up limit?
Thanks
Thomas Geury

LabVIEW FPGA support

Respected Sir,
Is LabVIEW FPGA support for kit numbered ML-505 ( FPGA Type : Virtex 5 LX110T ) available or not ? If yes, where it is?
Solved!
Go to Solution.

The only FPGAs that are supported by LabVIEW FPGA are the ones included in National Instruments hardware. You cannot target other FPGA kits using LabVIEW.

FPGA Poission Random Number

Hello,
I have Xilinix Virtex 5 FPGA and i want to implement poisson random number generator.
FPGA works at 100 MHz clock and at every cycle it should calculate poisson random number. Mean value of poisson distribution can change at every clock cycle. I want to make random time pulse generator with possion distribution. Pulse rate can vary between 1 and 1 billion pulses per second.
How i can make this generator? Please, help

b,
There are two kinds of randomn number generators that are commonly implemented in a FPGA device: a true random number generator (very hard to do), and a pseudo random number generator (trival to do).
The pseudo random generator is done using linear feedback shift registers, and its statistics are well understood, and do not vary (in fact, the sequence repeats depending on the length of the LFSR).
Attached is a form of true random number generator.
To get a specific distribution (e.g. Poisson) you would need to verify and [perhaps filter the genberated numbers.
Poisson being as close to radomn as possible (for example, radioactive decay times are Poisson distributed), a true randomn number generator is where I would start (the attachment).

Compilation error - FPGA NI PXI-7951R board - ERROR: Xst: 2472 - Top module Puma15Top was not found.

I'm trying to compile a "user CLIP socket" for the NI PXI board - 7951R which has a Virtex-5 LX30 FPGA from Xilinx, but I got the bellow message from NI Compiler, this message is in error report Xilinx.log.
It says that module Puma15Top was not found.
But this module is a NI property and is automatically compiled by NI Compiler.
The compiler automatically generates these files (Puma15Top...) that are passed to the compiler of Xilinx. The Puma15Top files are in the path, i.e: C: \ NIFPGA \ compilation \ Told_F_I_CC5DC260 \ source_files.
This folder name is automatically generated by labview (Told_F_I_CC5DC260) for each different project or compilation.
So I have no way to configure in CLIP files where it'll be Puma15Top, once the path is automatically generated during compilation by Labview.
Does anyone have any idea how to solve this problem? Or have you experienced some like this?
Following error log:
### XstSynthesis ###
Puma15Top
Reading design: Puma15Top.prj
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/NIFPGA/jobs/Cm9xA8x_LaF6U1d/CLUC001_Conf.vhd" in Library work.
Entity <CLUC001_Conf> compiled.
Entity <CLUC001_Conf> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/NIFPGA/jobs/Cm9xA8x_LaF6U1d/CLUC001_CLIP.vhd" in Library work.
Entity <CLUC001_CLIP> compiled.
Entity <CLUC001_CLIP> (Architecture <rtl>) compiled.
Entity <CLUC001_CLIP> (Architecture <behavioral>) compiled.
ERROR:Xst:2472 - Top module <Puma15Top> was not found.
ERROR:Xst:2469 - Please specify the correct library via the -work_lib switch.
-->
Total memory usage is 149596 kilobytes
Number of errors   :    2 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)
Process "Synthesis" failed
Thanks in advanced!

Hi Guilherme,
Thanks your suggestion, I upgraded NI-RIO to 13.1.1 version but the problem persists, as shown below:
Project: T_old.lvproj
Target: F (RIO0, PXI-7951R)
Build Specification: I_2
Top level VI: I.vi
Compiling on local compile server
Compilation Tool: Xilinx 11.5
Start Time: 2/9/2014 18:03:51
Run when loaded to Fpga: FALSE
JobId: z8Cq8B4
Working Directory: C:\NIFPGA\compilation\Told_F_I2_F3177096
Compilation failed due to a Xilinx error.
Details:
ERROR:Xst:2472 - Top module <Puma15Top> was not found.
ERROR:Xst:2469 - Please specify the correct library via the -work_lib switch.
-->
Total memory usage is 149596 kilobytes
Number of errors   :    2 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)
Process "Synthesis" failed
Start Time: 18:03:51
End Time: 18:05:19
Total Time: 00:01:27,414
Best,
JEMP

Is the labview 8.2 compatible with FPGA (altera) thats ordering code is DK-DSP-3C120N ?

is the labview 8.2 compatible with FPGA (altera) thats ordering code is DK-DSP-3C120N ?

Hey Mouath,
The FPGA module only supports the following:
Virtex-II 3000
Virtex-II 1000
Spartan-3 1000
Spartan-3 2000
Virtex-5 LX30
Virtex-5 LX50
Virtex-5 LX85
Please refer to FPGAs - Under the Hood for further information.
Aashish M
Applications Engineer
National Instruments
http://www.ni.com/support/

A question about correct SEU in Virtex4 LX25 FPGA

I have a problem when I scrube the DSP, IOB, CLK, CLB using the data stored in the Flash to correct the SEU in Virtex4 LX25 FPGA. This is my flow chart:
step1: read the state register to verify the state register
step2:  read the control register to verify the control register
step3:  write a 32bit data to FAR register and read FAR register to virify the FAR register
step4:  scrube the DSP, IOB, CLK, CLB logic in the Virtex4 LX25 FPGA using the data stored in the Flash(I shield the LUT RAM and SRL16).
Problem: when the step4 is done, if I immediately implement the step1 the scrube programe can influence the CLB logic. But when the step4 is done, if I delay 0.1s to implement the step1 the scrube programe has no influence on CLB logic.
Is this means that I should wait a minute when I begin the next scrube process? Thank you in advance.

Hi Lesea, Virtex4 is not supported by Soft Error Mitigation (SEM) Core, and I need to protect the Virtex4 LX25 FPGA by simple scrubbing. The configuration management engine I designed is the same as that in Correcting Single-Event Upsets in Virtex-4 FPGA Configuration Memory. I also do the fault injection experiment, and the configuration management engine can correct the faults in the Virtex4 LX25 FPGA.
On my board: digital signal A---->encode---->D/A---->A/D---->decode---->digital signal B
When I don't scrubbing the FPGA, the signal B is always the same as the signal A, so I think my board and the software in the FPGA operate well. When I scrubbing the FPGA too frequently, the signal B is not always the same as signal A(I only scrubbing the DSP, IOB, CLK, and CLB logic and I shield the LUT RAM and SRL16 logic). So I think the problem is caused by my configuration management engine.
I also find that the time between two scrubbing process can not be too short. For instance, if I delay only several clks(2.3825MHz) before the next scrubbing process, the signal B is not always the same as the signal A. But if I delay 0.1s, 1s or 10s before the next scrubbing process, the signal B is always the same as the signal A. So how can I solve the problem? I can do experiment to find the minimal time between the two scrubbing process that have no influence on my software. I want to know what causes this problem. Thank you:)
Regards,
Zhiyuan Peng

Virtex6:Configuration data download to FPGA was not successful. DONE did not go high, please check your configuration setup and mode settings

Hello，everyone.
I am using virtex6 FPGA and trying to download mcs file to PROM and have failed.
I download .bit file to FPGA and succeed.
When i try to download .mcs file to PROM XCF128X-FTG64C(BPI Flash) and choose Slave SelectMAP Mode
and the process is about 68% it fails.
The message below the IMapct is as belows:
done.
PROGRESS_END - End Operation.
Elapsed time =      0 sec.
// *** BATCH CMD : identifyMPM
// *** BATCH CMD : assignFile -p 1 -file "C:/Users/Administrator/Desktop/TEST/LED/led.bit"
'1': Loading file 'C:/Users/Administrator/Desktop/TEST/LED/led.bit' ...
done.
INFO:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream stored in memory,
but the original bitstream file remains unchanged.
UserID read from the bitstream file = 0xFFFFFFFF.
INFO:iMPACT:501 - '1': Added Device xc6vlx240t successfully.
INFO:iMPACT - Current time: 2014/3/13 8:48:14
// *** BATCH CMD : Program -p 1
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 66000000.
Validating chain...
Boundary-scan chain validated successfully.
INFO:iMPACT - 1: Over-temperature condition detected! [ 230.52C > 120.00C]
1: Device Temperature: Current Reading: 230.52 C, Max. Reading: 230.52 C
1: VCCINT Supply: Current Reading:   2.997 V, Max. Reading:   2.997 V
1: VCCAUX Supply: Current Reading:   2.997 V, Max. Reading:   2.997 V
'1': Programming device...
Match_cycle = NoWait.
Match cycle: NoWait
LCK_cycle = NoWait.
LCK cycle: NoWait
done.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 1111 0111 1110 0100 1011 1100 0000
INFO:iMPACT:579 - '1': Completed downloading bit file to device.
INFO:iMPACT:188 - '1': Programming completed successfully.
Match_cycle = NoWait.
Match cycle: NoWait
LCK_cycle = NoWait.
LCK cycle: NoWait
INFO:iMPACT - '1': Checking done pin....done.
'1': Programmed successfully.
PROGRESS_END - End Operation.
Elapsed time =     23 sec.
Selected part: XCF128X
// *** BATCH CMD : attachflash -position 1 -bpi "XCF128X"
// *** BATCH CMD : assignfiletoattachedflash -position 1 -file "C:/Users/Administrator/Desktop/TEST/LED/leda.mcs"
INFO:iMPACT - Current time: 2014/3/13 8:49:32
// *** BATCH CMD : Program -p 1 -dataWidth 16 -rs1 NONE -rs0 NONE -bpionly -e -v -loadfpga
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 66000000.
Validating chain...
Boundary-scan chain validated successfully.
INFO:iMPACT - 1: Over-temperature condition detected! [ 230.52C > 120.00C]
1: Device Temperature: Current Reading: 230.52 C, Max. Reading: 230.52 C
1: VCCINT Supply: Current Reading:   2.997 V, Max. Reading:   2.997 V
1: VCCAUX Supply: Current Reading:   2.997 V, Max. Reading:   2.997 V
'1': BPI access core not detected. BPI access core will be downloaded to the device to enable operations.
INFO:iMPACT - Downloading core file D:/Xilinx/14.3/ISE_DS/ISE/virtex6/data/xc6vlx240t_jbpi.cor.
'1': Downloading core...
Match_cycle = NoWait.
Match cycle: NoWait
LCK_cycle = NoWait.
LCK cycle: NoWait
done.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 1111 0111 1110 0100 1011 1100 0000
INFO:iMPACT:2492 - '1': Completed downloading core to device.
Current cable speed is set to 6.000 Mhz.
Cable speed is default to 3Mhz or lower for BPI operations.
Current cable speed is set to 3.000 Mhz.
Setting Flash Control Pins ...
Setting Configuration Register ...
Populating BPI common flash interface ...
Common Flash Interface Information Query completed successfully.
INFO:iMPACT - Common Flash Interface Information from Device:
INFO:iMPACT - Verification string: 51 52 59
INFO:iMPACT - Manufacturer ID:        49
INFO:iMPACT - Vendor ID:             01
INFO:iMPACT - Device Code:           18
Setting Flash Control Pins ...
Using x16 mode ...
Setting Flash Control Pins ...
Setting Configuration Register ...
'1': Erasing device...
'1': Start address = 0x00000000, End address = 0x008CE03B.
done.
'1': Erasure completed successfully.
Setting Flash Control Pins ...
Using x16 mode ...
Setting Flash Control Pins ...
Setting Configuration Register ...
INFO:iMPACT - Using Word Programming.
'1': Programming Flash.
done.
Setting Flash Control Pins ...
'1': Flash Programming completed successfully.
Using x16 mode ...
Setting Flash Control Pins ...
Setting Configuration Register ...
'1': Reading device contents...
done.
'1': Verification completed.
Setting Flash Control Pins ...
Current cable speed is resumed to 6.000 Mhz.
'1': Configuration data download to FPGA was not successful. DONE did not go high, please check your configuration setup and mode settings.
`Elapsed time =    814 sec.
and i find many people have met the same thing. But they are spartan series FPGA and i try to low the Resistances of Mode pins,M0 M1 and M2, but the problem does not been solved.
I have read the status Registers and find there is an over-temperature state
and in Impact i could not readback the registers. It is strange.
I am anxious about this problem and have not solved it yet
What reasons may it be?
Hope for your answer, thank you

Hi~I want to know if you solve the configuration problem for virtex-6?
As I encounter the  same configuration problem, I want to consult  you with some question.
Can I have your email?
gszakacs wrote:
I have measured the VCCINT and find it is 1.0V, not 2.997V;
That is not at all surprising. I always assumed the problem is with reading the XADC (system monitor) block and not with the voltage or temperature.
my Reference board is ML605
That would have been nice to know at the beginning...
It seems that you have selected the correct mode, assuming your jumpers are set as required in the ML605 Hardware User's Guide. See table 1-27, table 1-33 and the note below it about switch S1.
I'm not that familiar with the details of this reference design, but it may be that the slave SelectMap circuitry requires a reset or power cycle to actually configure the FPGA. Have you tried power-cycling to see if the FPGA boots from the flash?
I'd also suggest that you select the V6 in the JTAG chain view, then go to the debug menu of Impact and select Read Device Status (this is from memory, but it's something like that). That will not only show the bits of the configuration status register, but also describe what each bit means. Among other things you can check the state of the FPGA's configuration logic and the Mode pins.

OpenSPARCT1 on Virtex-7

Hi,
I am trying to implement OpenSPARCT1 on Xilinx Virtex-7(VC707 XC7VX485T-2FFG1761CES Evaluation Board), single core and multi core. I first tried the EDK project on Virtex-5 and now I want to check feasibility of implementation of the same on Virtex-7. But I am facing a few problems as below:
1. Generating NGC netlist for Virtex-7 - For rxil command, the OpenSPARCT1 package does not contain the .xst file for my Virtex-7 device. How can I create one or modify the others for my FPGA? Also I tried creating a project on ISE 13.4 and added a copy of all the files mentioned in /design/sys/iop/sparc/xst/sparc.flist but the synthesis is not running due to many missing files and unrecognized modules.
2. I earlier implemented the EDK project on Xilinx EDK 10.1. How can I make it run using Xilinx EDK 13.4? Previously it showed the error - ERROR:EDK:3548 - Revup to 13.4 failed
ERROR:EDK:3413 - Error(s) were encountered while updating your project.
Any inputs for solutions to the above problems would be highly appreciated.
Thanks
pk21

Hi,
I found a solution to my problem. I created a .xst file for virtex-7 device by copying device parameters given in a random ISE and I was able to generate the bit file for single-core 4-thread. It uses hardly 18½ LUT resources.
But still the EDK problem persists, if anyone has a solution, please contribute.
Also has anybody tried to implement a dual-core on single FPGA? I am trying to generate bit-file for dual core but I am not able to find options to do so. Please help!!
Thanks in advance

Feedback nodes / delays and Resource Usage on FPGA

Again it's time for an exotic FPGA semi-noob question from myself.
This has been bugging me for a long time:
When implementing a delay stage on a Virtex-5 target, we have a few options available.
Feedback nodes : Uses LUTs. Virtex 5 has 6-input LUTs. Does this mean that a Feedback node with delay 1 requires the same resources as a Feedback node with delay 6 and a Feedback node with delay 7 requires double the LUTs as one with delay 6?
Example: A single unit delay feedback node for a U16 requires 16 LUTs. What is the LUT usage for 6, 7, 9 delay?
BRAM : Uses few LUTs and Registers. I reckon I understand this one.
Discrete Delay : Can't be used as feedback but is more efficient than feedback nodes? It is written in the help that feedback nodes with the reset support disabled CAN be implemented as SRLs allowing the compiler to choose th ebest option whereas the Discrete Delay primitive forces an SRL Is the SRL implemented using LUTs?.
Which of these options is recommended for which purpose. We're really filling our chip and need to start considering such aspects of number storage.
Sorry for the over-reaching vague questions again.
On the other hand, being on a steep learning curve is actually almost thrilling. Every bit of information helps me learn so thanks for that in advance.
Shane
Say hello to my little friend.
RFC 2323 FHE-Compliant

JLewis wrote:
The number of inputs is only indirectly related to the supported delay. The V-5 and above CLBs (Configurable Logic Blocks) can be configured as dedicated shift registers with delays up to 32 in a single LUT per bit. The main restriction is that these shift registers are not resettable, so you only get this implementation when configured without an initialization value. Delays above 32 can be efficiently implemented in multiple LUTs (ie, 1 LUT per 32 delay). These shift registers are known as SRL16 or SRL32, depending on the target family.
So does this mean that on a LUT-basis, a shift register (with the reset conditions met) with a delay between 1 and 32 costs the same amount of resources? 33-64 delay costs twise that of a single delay? Is this correct? I think I need some benchmarking code.....
JLewis wrote:
Discrete Delay maps to the same shift register implementation as feedback nodes if the reset condition is met. Otherwise, the main difference is that the Discrete Delay exposes the dynamic delay feature available in the hardware shift registers and, as you noted, can't be used in a feedback cycle. If neither of those considerations is a factor in your design, it's just a matter of preference.
This document from Xilinx contains the keys to the kingdom, as far as what hardware capabilities are available: http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
That's kind of what I thought.
JLewis wrote:
Hi Shane,
Great questions!
Well thank you, Thanks for the answers.
Say hello to my little friend.
RFC 2323 FHE-Compliant

Is there an obvious way to prevent an FPGA multiply from using DSPs?

In FPGA coding a High Throughput Multiply function will take advantage of any available DSPs on your FPGA. This is great, unless you have more multipliers than available DSPs. My FPGA code is currently failing to fit, and although it's using just 50% of the Registers/Slices, it's trying to use more DSPs than are available (My Virtex 5 chip has 64 DSPs).
In the help I'm pretty sure it says the compiler will revert to using slices for multiplications in the absence of sufficient DSPs, but my experience is otherwise.
If I convert just one of the High Throughput Multiply functions to a standard LabVIEW Math multiply primitive I receive timing errors from the compiler (even though there are minimal timing constraints in my code), and it therefore still fails to compile.
So my question is: Is there a way to prevent a Multiply function in LabVIEW FPGA from using DSPs?
Thoric (CLA, CLED, CTD and LabVIEW Champion)

Dragis wrote:
Unfortunately, this is a bug/feature of the Xilinx tools. Once the tools have decided to choose DSP blocks for the multipliers, it will only use them and not place any in logic. There is a way to disable automatic usage of DSP blocks, you'll have to work with NI customer support to make that change. If you use this option, you'll have to manually drop the High Throughput Multiplier everywhere you want a DSP48 to be used.
I've gone through Technical Support with this issue once before about a year ago and there was no mention of a 'solution', just the unhelpful suggestion to "use fewer multipliers". I'll raise another support case and link to this thread, maybe they'll need to speak with you directly to understand what this option is.
I'm perfectly happy, in fact I'd prefer, to be able to specifically select where a DSP is and isn't used for a multiplication. If reasonable, I'd suggest this option to disable automatic usage of DSPs be made public (either through the knowledgebase, or as an actual feature in the FPGA toolkit perhaps).
Thanks Dragis.
Thoric (CLA, CLED, CTD and LabVIEW Champion)

FPGA Virtex 2 pro

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