LabVIEW FPGA support

Respected Sir,
Is LabVIEW FPGA support for kit numbered ML-505 ( FPGA Type : Virtex 5 LX110T ) available or not ? If yes, where it is?
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The only FPGAs that are supported by LabVIEW FPGA are the ones included in National Instruments hardware. You cannot target other FPGA kits using LabVIEW.

Similar Messages

Does LabView 2013 supports spartan 3E FPGA

Hi,
whether Labview 2013 supports spartan 3E driver.
i could not able to find drivers for that.
Else, i have procured Xilinx XUP V5 board.
can i use the virtex 5 board with labview 2013. for that any driver is there...

T-REX$ wrote:
Hey mangood,
There currently is no support for the Spartan3E board in LabVIEW FPGA 2013, and I am not aware of any plan for developing support in the near future. Sorry for the bad news...
DEAR
i have lab view 2012 and it has device drvie for spartan FPGA
only one year
may be can NI do this its simple
thank
hi ?Q>

How do I install Labview 64 bit support for the labview fpga module?

see subject.

Hi,
The LabVIEW FPGA Module uses the 32-bit version of the Xilinx tools, even on the 64-bit OS.
There is no 64 bit version of LabVIEW FPGA and you must have LabVIEW 32 bit
installed on your 64-bit machine to use the compatible version of
LabVIEW FPGA.
NI LabVIEW FPGA Module will run within the 32-bit emulation layer, Windows on Windows (WOW64).
regards,
Houssam Kassri
NI Germany

How can I install (download) a Labview FPGA code onto Altera FPGA chip using Labview FPGA module?

Hi there
Guys i'm a very new labview user (PhD student), my project is about ( design and implementation of a high speed-yet sophisticated system using Labview environment then install this project's code (using Labview FPGA module) onto Altera-made FPGA chip).
so kindly, can any body help me in this?...is there any way to connect labview with Altera FPGA?...please anything would be said 'd be of great benifits
thanks a lot in advance.

as previously mentioned, labview fpga only supports national instruments targets utilizing xilinx fpgas. the hdl generated by labview fpga is encrypted and cannot be used to synthesize a design outside the labview fpga design flow.
however, if you must use labview for your project, it might be possible for you to design the system in labview and use one of the labview embedded modules ( http://www.ni.com/embedded )to generate c code which you can then port to systemc and compile for the altera fpga. i'm not saying it will be easy, but it should be possible.

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
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Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

Labview fpga module 8.6

I want use labview FPGA modul 8.6 can somebody help me to dowlaond this modul thanks

Hi scream,
It would best contact your account representative within National Instruments, they will be able to determine how to best deliver this module to you. Thanks!
Matt S.
Industrial Communications Product Support Engineer
National Instruments

Labview fpga module Spartan 6 LX9 FPGA

Does Spartan 6 LX9 FPGA supported in labview FPGA module ?

varunme,
The only FPGA targets that can be programmed with LabVIEW FPGA are National Instruments FPGA products (cRIO, sbRIO, R-Series, FlexRIO, etc) and the Xilinx Spartan 3E XUP board. Unfortunately, LabVIEW FPGA doesn't support third party devices containing the LX9 FPGA.
-Nick-
Nick C | Staff LabVIEW Platform Product Support Engineer | National Instruments

LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred

Hi,
I am trying to build a LabView FPGA VI. During compilation, I always get error stating "LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support". At the time, comiplation process is almost at the end. "Final Timing (place and route)" shows as completed. When Checked the Xilinx log session, at the end it states that " Process "Generate Programming File" completed successfully". However, I do not see any generated bitfile.
When clicked on error details, it shows following:
LabVIEW: An unknown error occurred.
Error -2629 occurred at Error occurred while loading XML string. Invoke Node in niFpgaXml_PrettyPrint.vi->niFpgaWriteBitfileXml_Core.vi->niFpgaCompileWorker_CreateBitfile.vi->niFpgaCompileWorker_JobComplete.vi->niFpgaCompile_Worker.vi:6460001
Possible reason(s):
LabVIEW: An unknown error occurred.
I tried multiple times but so far no luck to generate bitfile for this VI. What could be wrong here?
I am using Labview 2013

Hi Mark,
Here is the device utilization Summary. My development system is running with Windows-7 (32 bit) with 3GB RAM and Labview 2013.
Device Utilization
Total Slices: 90.0% (11970 out of 13300)
Slice Registers: 40.7% (43258 out of 106400)
Slice LUTs: 71.6% (38103 out of 53200)
DSP48s: 1.4% (3 out of 220)
Block RAMs: 22.1% (31 out of 140)
Timing
40 MHz Onboard Clock
: 40.00 MHz (57.90 MHz maximum)
80MHz (Used by non-diagram components)
: 80.00 MHz (100.19 MHz maximum)
--WillsG

DCT for Labview fpga

Hi,
I have problems based on dct for labview fpga. I get the project example from this link https://decibel.ni.com/content/docs/DOC-8202. I run the project in labview and its run succesfully. After that, I try to use a different vhdl code for the CLIP (in labview) that I get from open cores (http://opencores.org/project,dct_idct). I rewrite the fpga.vi by inserting a new vhdl code in the CLIP. When I run the project, there are no errors. However, the compressed image is not display. I check the output values from the Read from FPGA block at the host.vi and it shows zero values at all time. I try to debug, but still don't get the solution. Anyone expert please help me. Thanks in advance.

Hey Troy,
Have a look at the attached front panel design that will be compatible in FPGA.
Hopefully it helps!!
Aashish M
Applications Engineer
National Instruments
http://www.ni.com/support/
Attachments:
FPGA_CALC.vi ‏22 KB

Labview 2010 Student Edition, will it work with the Labview FPGA module and Xilinx Spartan 3E??

Just as the title states.
I did a search here on compatibility, but I am coming up short with not much to show for it.
I have Labview 2010 student edition, 32bit and 64 bit. I am trying to do a Senior Design project for my undergrad, and I am having some issues.
I was able to download the Support for the Xilinx Spartan 3E and Labview FPGA.
I install it, it runs through the unzipping process, installs, and then mysteriously I cannot find it. I have looked through my programs list and it is not listed. I open both editions of LabView and I find ABSOLUTELY NOTHING indicating that either one has ANYTHING to do with FPGA.
Did I install it wrong? Or is it just not supported in the studend version of Labview???
Can someone help me, please?

M Boat wrote:
What about the trial version? Any chance of it being on there?
I think everything is available for download, and without activation it will be in trial mode and you have about a month (?) before the trial expires.
A trial version of the FPGA module is available for download here. I have no idea if it would work with the student version.
I would recommend to talk to your local NI sales representative for advice. Good luck.
LabVIEW Champion . Do more with less code and in less time .

CanOPEN cRIO-9067 & LabVIEW 2014 support

Hello,
We have cRIO-9067 and NI 9881 CANOpen communication module.
According to the NI 9881 product description page the module should work with cRIO-9067. However, the latest NI-Industrial Communications for CANopen 1.0.3 doesn't support LabVIEW 2014 and NI RIO 14.0. This means we can't use cRIO-9067, can we? If so, when the next release of the driver will be availiable? Will it work with cRIO-9030?
Thank you in advance,
Nikita.
Nikita Prorekhin
Certified LabVIEW Developer
DigiMetrix GmbH
web www.digimetrix.com
Solved!
Go to Solution.

Hi Nikita,
This is an error on the webpage. Currently, it should actually read:
The NI 9881 module requires the NI cRIO-911x/9068/908x chassis and the LabVIEW FPGA Module.
Support for the 906x and 903x targets will come with the NI-Industrial Communications for CANopen 14.5. Typically, the release is around the time of the LabVIEW 2014 SP1 release. I apologize for the inconvenience, and have reported this to the person in charge of the page to correct this error.
Thank you!
Matt S.
Industrial Communications Product Support Engineer
National Instruments

NI 9512 with Labview FPGA Interface

Is it possible to use the NI 9512 stepper drive module with the Labview FPGA interface or is it only possible to use it with the scan interface? When I try to add the module to an FPGA target, I get an error telling me that Labview FPGA does not support this module with the current version of NI-RIO, but I have the latest version of NI-RIO installed.
Solved!
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Hi RJ12,
Thank you for the info!
If this problem is holding you up you should give our Applications Engineering department a call at 866-275-6964 to discuss it. The 9076 can have some compilation compatibility issues with our motion modules so it's certainly possible you could be seeing such an error.
Feel free to get in touch with us if we can help out in any way, or consider starting a new thread with more details on the compilation error if you'd like to see if a corrective action report (CAR) already exists.
Best regards,
Andy C.
Applications Engineering
National Instruments

Edge triggered D flip flop in labview fpga

Hi,
I am trying to write a program to test ADC with PXI-7962 FPGA. This is basically a 9 bit SAR ADC whose data is to be read every time a 100 MHz clock have a positive or nagative edge. So I have to check for edges in the clock and take the value of the 9 bits in that same instant, for which I need edge triggered D flip flops. But I could not find any D flip flop on the FPGA functions pallette and also could not find a good solution in the web. Can anybody help me in this regard?
Thanks,
Anindya

I would recommend giving yourself a foundation in labview if this is going to be a sustained development effort. The best way to do this is with instuctor led training. If that isn't an option then the next best thing is self paced online training, which is free if you have purchased LabVIEW or LabVIEW FPGA.
Strengthen Your Core with the New Self-Paced Online Training
https://decibel.ni.com/content/docs/DOC-32313
The advantage to giving yourself a foundation is you learn to ask the right questions earlier in development. The folks on the forums can only answer the questions you are asking, and while acessing every bit in a numeric is a perfectly reasonable question, we have no idea if what you are trying to do with them is reasonable and if accessing them all is even necessarry for your application.
National Instruments
FlexRIO Product Support Engineer

HELP -FPGA SPARTAN 3E-100 CP132 WORKS WITH LABVIEW FPGA ?

HI EVERYBODY, IM TRYING TO USE MY FPGA BOARD WITH LABVIEW, BUT I DONT KNOW THAT IF ITS COMPATIBLE, I INSTALLED DRIVERS, FPGA MODULE, AND LABVIEW 2012, IM USING WINDOWS 7 32 BITS, AND AFTER I COMPILE ITS SAID :
LabVIEW FPGA called another software component, and that component returned the following error:
Error Code: -310601
NI-COBS: Unable to detect communication cable.
Please verify that the communication cable is plugged securely into your computer and target. Also verify that the appropriate drivers are installed.
THANK YOU .
=)
Solved!
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Hi dvaldez2.
LabVIEW FPGA does not offer support for any third party hardware, other than the Spartan 3E XUP Starter Kit. Those are probably the drivers you downloaded.
http://digital.ni.com/express.nsf/bycode/spartan3e?opendocument&lang=en&node=seminar_US
However, this driver only supports the Starter Kit board itself (http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,790&Prod=S3EBOARD). You can't use the driver with any other FPGA from Xilinx.
Hope this helps.
Aldo H
Ingenieria de Aplicaciones

Why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?

Dear Friends,
Since I have started using LABVIEW FPGA, I got too many questions in my mind looking for answers!
1-      Does anybody can tell me “why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?”
I mean there are many great tools in this field (e.g. Xilinx ISE, ….); what makes LABVIEW FPGA the perfect tools that can save my time and my money?
I’m looking for a comparison can show the following points:
·         The Code size and speed optimization.
·         Developing time.
·         Compiling time.
·         Verifying time.
·         Ability to developing in future.
·         …etc.. 2-
I’ve Spartan-3E kit, I’m so glad that LABVIEW support this kit; I do enjoyed programming the kit using LABVIEW FPGA, but there are too many obstacles!
The examples come with Spartan-3E driver don't cover all peripherals on board (e.g. LAN port is not covered)! There is a declaration at NI website which is "LabVIEW FPGA drivers and examples for all on-board resources" Located at: http://digital.ni.com/express.nsf/bycode/spartan3eI don’t think that is true!
Anyway, I will try to develop examples for the unsupported peripherals, but if the Pins of these peripherals are not defined in the UCF file, the effort is worthless! The only solution in this case is to develop VHDL code in ISE and use it in Labview FPGA using HDL node!?
3-      I wonder if NI has any plan to add support for Processor setup in Labview FPGA (Like we do in EDK)?
4-      I wonder if NI has any plan to develop a driver for Virtex-5 OpenSPARC Evaluation Platform ?http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,599&Prod=XUPV5
Thnaks & regards,Walid
Solved!
Go to Solution.

Thanks for your questions and I hope I can answer them appropriately
1. LabVIEW FPGA utilizes the intuitive graphical dataflow language of LabVIEW to target FPGA technology. LabVIEW is particularly nice for FPGA programming because of its ability to represent parallelism inherent to FPGAs. It also serves as a software-like programming experience with loops and structures which has become a focus of industry lately with C-to-gates and other abstraction efforts. Here are some general comparison along the vectors you mentioned
Code Size and speed optimization - LabVIEW FPGA is a programming language. As such, one can program badly and create designs that are too big to fit on a chip and too slow to meet timing. However, there are two main programming paradigms which you can use. The normal LabVIEW dataflow programming (meaning outside a single-cycle loop) adds registers in order to enforce dataflow and synchronization in parity with the LabVIEW model of computation. As with any abstraction, this use of registers is logic necessary to enforce LabVIEW dataflow and might not be what an expert HDL programmer would create. You trade off the simplicity of LabVIEW dataflow in this case. On the other hand, when you program inside a Single-Cycle timed loop you can achieve size and speed efficiencies comparable to many VHDL implementations. We have had many users that understand that way LabVIEW is transformed to hardware and program in such a way to create very efficient and complex systems.
Development Time - Compared to VHDL many of our users get near infinite improvements in development time due to the fact that they do not know (nor do they have to know) VHDL or Verilog. Someone who knows LabVIEW can now reach the speeds and parallelism afforded by FPGAs without learning a new language. For harware engineers (that might actually have an alternative to LabVIEW) there are still extreme time saving aspects of LabVIEW including ready-made I/O interfaces, Simple FIFO DMA transfers, stichable IP blocks, and visualizable parallism. I talk to many hardware engineers that are able to drastically improve development time with LabVIEW, especially since they are more knowledgable about the target hardware.
Compilation Time - Comparable to slightly longer to due to the extra step of generating intermediate files from the LabVIEW diagram, and the increased level of hierarchy in the design to handle abstraction.
Verification Time - One of our key development initiatives moving forward is increased debugging capabilities. Today we have the abilities to functionally simulate anything included in LabVIEW FPGA, and we recently added simluation capabilities for Imported IP through the IP Integration node on NI Labs and the ability to excite your design with simulated I/O. This functional simualation is very fast and is great for verification and quick-turn design iteration. However, we still want to provide more debugging from the timing prespective with better cycle-accurate simulation. Although significantly slower than functional simulation. Cycle-accuracy give us the next level of verification before compilation. The single cycle loop running in emulation mode is cycle accurate simluation, but we want more system level simulation moving forwrad. Finally, we have worked to import things like Xilinx chipscope (soon to be on NI Labs) for on-chip debugging, which is the final step in the verification process. In terms of verification time there are aspects (like functional simulation) that are faster than traditional methods and others that are comparable, and still other that we are continuing to refine.
Ability to develop in the future - I am not sure what you mean here but we are certainly continuing to activiely develop on the RIO platform which includes FPGA as the key diffentiating technolgoy.  If you take a look at the NI Week keynote videos (ni.com/niweek) there is no doubt from both Day 1 and Day 2 that FPGA will be an important well maintained platform for many years to come.
2. Apologies for the statement in the document. The sentence should read that there are example for most board resources.
3. We do have plans to support a processor on the FPGA through LabVIEW FPGA. In fact, you will see technology on NI Labs soon that addresses this with MicroBlaze.
4. We do not currently have plans to support any other evaluation platforms. This support was created for our counterparts in the academic space to have a platform to learn the basics of digital design on a board that many schools already have in house. We are currently foccussing on rounding out more of our off-the-shelf platform with new PCI Express R Series boards, FlexRIO with new adapter modules, cRIO with new Virtex 5 backplanes, and more.
I hope this has anwered some of the questions you have.
Regards
Rick Kuhlman | LabVIEW FPGA Product Manager | National Instruments | ni.com/fpga
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