Freeing DMA channels

I am using pattern gen. single buf. input on a 6533 with Win2k and Borland C++ v5. When the program using the board (via NI-DAQ, the latest version) dies badly, it does not seem to free the DMA channel that the board is using. I get the "No DMA channel available for use" error when I run my program again. This means that I have to reboot.
How can I free the DMA channel used by the 6533 without rebooting? I have tried to use DIG_Block_Clear at the start of my program, but it complains that no transfer is in progress.

DAQ_Clear is for DAQ devices, not DIO devices. I get an error -10403 "Device does not support the requested action" when I try this function.
BTW: I mistankenly said I had a 6533; I actually have a PCI-DIO-32HS (they are pretty much the same thing, the 32HS uses PCI instead of PXI).

Similar Messages

Dma channel problems

Hello,
I really need help on this one. Using PCI-6035E I am trying to output an analog signal (actually 2 waverforms interleaved together) on 2 channels while simultaneously using the two GPCTRs to measure two separate signals' pulse widths. The VI runs perfectly on some occasions, while on others I get "no DMA channel available for use". Whenever this message appears and I try to exit labview, the nipalk.sys driver messes up and I get a blue screen crash that says "process_has_locked_pages" (I traced the locked pages to this driver). I've tested this many times and it appears to me to be totally random. I've used the Set DAQ device information VI to set the two counters to use interrupts, but I need to use the one DMA channel for
the analog output. My best guess is that there is some kind of resource conflict with something else in the PC, but I can't figure out how to change DMA assignments(I'm using Windows XP). The NI-DAQ Measurement and Automation Explorer tells me that the card is using DMA 0, IRQ 17. I've tried uninstalling all the NI-DAQ drivers, reinstalling and updating. Any help anybody could give me would be greatly appreciated.
Thanks,
Nick
Attachments:
aug7.vi ‏374 KB

Hello;
The PCI bus has 3 DMA channels that are share in between all devices that do DMA data transfers.There is nothing you can do to change that, since that is a PCI bus feature.
The best way to go about that is to remove other devices that use DMA, such as network cards, for instance. That might free up more DMA access time for your DAQ device to execute its data trasnfers.
Hope this helps.
Filipe A.
Applications Engineer
National Instruments

X Series DDK: Configure Interrupt on DMA Channel's total transfer count

Hello,
In the DAQ-STC3 X Series DDK Reference Manual, Chapter 1: Theroy of Operation, Section Interrupts, Subsection Special Considerations: Maximizing Throughput in Low-Latency Situations (p41), it is said:
"for X Series devices, the CHInCh can interrupt on the DMA channel’s total transfer count, which occurs once the data has been completely transferred to the host memory. The order of programming for this situation (and output operations) is as follows:
1. Program the DMA channel’s Total_Transfer_Count_Compare_Register (CHTTCCR) with the number of Bytes in a single input/output sample.
2. Set the DMA channel’s Notify on Total Count flag in the CHCR.
3. Set the DMA channel’s Arm Total Count Interrupt flag in the CHOR.
4. Start data transfer (through the DMA controller and the subsystem’s Stream Circuit).
5. Receive total transfer count interrupt.
6. Increase the CHTTCCR by the number of Bytes in a single input/output sample.
7. Re-arm the total transfer count interrupt in the CHOR.
Using the X Series DDK, I don't manage to perform such a configuration.
Can you please provide me code sample to do so ?
Thanks in advance for your support.
Sincerely
Bertrand

Hello Steve,
Weeks ago, we developed a Linux application that configure NI acquisition board (serie X) to send an interrupt when FIFO count reach a given number. At this stage we manage to prove that our board configuration was good and that the problem was due to INtime. TenAsys (INtime developers) fix this issue few weeks ago.
We just come back from holidays, apply the modifications created by TenAsys and manage to get interrupt inside INtime.
We still have two problems.
Reading DMA
===========
From the interrupt handler, when we access to the DMA to get samples stored in the FIFO, we manage to get the samples inside the first interrupt handler. With the following interrupts, when accessing DMA with the tCHInChDMAChannel structure, it said that there is no available bytes. But when we read the Channel_Total_Transfer_Count_Status_Register from the DMA channel, we see that we have the desired numbers of samples.
In the interrupt handler, during the interrupt aknowledgement, instead of only reading the Volatile_Interrupt_Status_Register to ackowledge the interrupt, if I increase the Channel_Total_Transfer_Count_Compare_Register_LSW by a given number (X) then I got X samples to read in the following interrupt. Problem with this solution is that the delay between two interrupts is not constant.
It seems that we mis-configured the DMA channel. But don't manage to find the error.
Two interrupts generated
====================
Moreover, we always get 2 FIFO_Count interrupts. Even configuring conversion, sampling and interrupt frequencies at very low value (conversion 1KHz, sampling 1Hz, interrupt generation: 1Hz). The delay between the two interrupts is about few nano seconds.
Source code
============
I attach to this post the source code we use to play/test this configuration. There is a Visual Studio workspace that we used to play with INtime and a CMake configuration file that we used to manage our Linux tests. You can find all the informations you need to build the binary in the README file.
Thanks in advance for your help with these issues.
Sincerely
Bertrand Cachet
Attachments:
IOMonitoring.zip ‏355 KB

Finite Measure with 2 boards 6602 and 6 DMA Channel Counter Buffered - error 200141

Hi all,
First .. I'm a beginner with LabView and I hope to explane myself in good way cause I'm italian..
I red all the post about the error 200141 and check the suggested solutions (also the way to ignore the error), but I want try to ask for a differet one..
What i'm trying to do is to aquire 6 encoder, 3 on the first board PCI 6602 and 3 encoder on the second board on DMA channels.
The encoder generate 90000 X4 = 360000 pulses x revolution and the max speed rotaion is 4 RPs.
Cause I need to store in a bin file all the pulses from the encoders, i generate a trigger of 1.5 MHz to get all the samples at the max system speed (360000 * 4 = 1440000 pulses x sec).
I think to have reached the limit, and maybe is not possible do better.. actually the 2 PCI 6602 works with 1,0 MHz of trigger and the system store in 6 files 4000000 of samples during
the finite measure of the angular position on 6 channels.
The trigger is not yet sync between the 2 PCI cause I'm waiting for a RTSI cable to put in the PC...
In Your opinion is possible to find a alternative way to acquire these encoders ?..
Thanks

I also doubt if you need to capture every single increment from each encoder. I'll discuss this more below.
Further, many earlier discussions suggest that counter tasks can sustain data transfers merely in the 100's of kHz, with *maybe* a possibility under special circumstances to slightly exceed 1 MHz. Your boards have very small hardware buffers (either 1 or 2 samples worth), causing the PCI bus usage to be very frequent and therefore less efficient.
Now, let's go back to your sample rate. You've got encoders which suggests that you're dealing with a physical system. Physical systems have inertia, which limits their useful bandwidth. In my experience, it's quite unusual to care about motion artifacts beyond the 10's of kHz. The inertia just doesn't allow anything significant to happen at that rate.
So, if the physical bandwidth of your motion system is, say, 5 kHz, there's a rule of thumb suggesting to measure at 10x when possible. So that'd mean 50 kHz sampling. 50 kHz x 6 channels on the PCI bus may be possible. Multi-MHz sampling won't be.
Can you describe the physical system a bit?
-Kevin P.

Number of DMA Channel on System

I need to log 16 (my be 32 later) simultaneous channel at the same time.
Is the limit of DMA chanels a windows system problem or just a card problem?
I understand that there is a limited number depending on the operating system.
So I cannot use 4 6601E cards (4 chanels each)at the same time on a PC.
I am told my NI that I could us PXI rack with a number of 6115 cards and an embeded controller running Window but I can not see that this would resolve the DMA problem unless it was a modified window system.
The other problem I see is that if Window 2000 or XP configers the cards to use he same chanel, Window will not let you change anything youself as all seeting are allway grayed out.
Judging my the large number of post on DMA perha
ps NI should write a white paper detaiing all the problems.
Thanks in advance fr your help.
Colin

Hello Colin,
Back with the ISA boards the limit of DMA channels was due to the computer itself. Now with PCI, DMA is handled by the PCI board itself. There has to be separate DMA controller hardware for each DMA channel. Our controller chip suppports up to 3 DMA channels. So I wouldn't say that this is a problem really. It's simply what the card offers, similar to the number of counters that is on the board.
There are fewer DMA channels than counters because 1) more DMA controllers would be more expensive, 2) Most applications probably would not require DMA channels for every counter. Interrupts may be sufficient for slower acquisitions or the the counters may be used for pulse generation which also wouldn't require DMA.
I guess I don't know enough abo
ut your application to comment on the 6115 suggestion. The 6115 is an analog simultaneous sampling board, but they only have 2 counters each. Perhaps it was suggested that you acquire this data with analog sampling. The advantage to this is that you can use the same DMA channel for all analog channels being scanned which would probably be a good alternative for your application.
Russell
Applications Engineer
National Instruments
http://www.ni.com/support

How many DMA Channels does my device have?

I would like to know how I can find out (progammatically) how many DMA channels my device has. I am using the DAQmx driver. Other than with the traditional DAQ I can't find out anything about my device but the "type" and the "serial number". Where can I get some more details about the device (not in the MAX - I want to know it in my program) with DAQmx?
My intention is to find out how many DMA Channels the device has and depending on how many Channels I need - I am using "interrupts" instead of DMA.
Somewhere in the KB of Ni was written that the NI-DAQ 6.9.... realizes automatically how many DMA Channels are available and how many I would need - and so he takes "interrupts" for the rest.
It seems that they did a "step bac
kwards" because with the NI-DAQ 7.2 it doesn't work automatically if I need DAQmx VI's.
Does somebody know anything that would help me to solve this problem?
Thanks.

Sorry! I posted my first revision of the answer.
Here is what I meant to say:
Hello,
According to this KnowledgeBase, DAQmx and Traditional DAQ behave the same. Are you seeing something different?
As far as a workaround goes, all you have to do is trap the No DMA error. This error should be -200251. So in software, if you receive error -200251, then you need to configure the board to use interrupts, and then start the task again.
How to configure the board for interrupts differs from the four different DAQmx API�s (C, C++, DotNET, and LabVIEW). If you are unclear about how to do this in your environment, please let us know, and we can find
out.
Best regards,
Justin T.
National Instruments

Number of DMA channels

如題，
我手邊有9636/9633兩張卡，
手冊上都是寫Number of DMA channels=5
請問這個數量跟FIFO Target to host DMA是一樣的意思嗎?
因為我設超過3個FIFO Target to host DMA，就會出現錯誤。
還有FPGA的FIFO最大個數是多少?
因為設3個FIFO Target to host DMA+2個FIFO Target scoped
有時候可以過，有時不行，有時程式還會閃退，真是OOXX
附件:
2013-05-30_151309.jpg ‏45 KB

http://www.ni.com/pdf/manuals/372596b.pdf
Number of DMA channels
http://digital.ni.com/public.nsf/allkb/22E2CE79F77B27508625794C00188265
http://digital.ni.com/public.nsf/allkb/470FF5EE8FD677F58625760A007562B9
您的應用為何?

Using ni-daq 7.1 traditional for AT-AI-16XE-10 first DMA channel doesn't respond

when using ni-daq 6.9.3 with AT-AI-16XE-10 it works OK!.using ni-daq 7.1 traditional first DMA channel does not respond.help please!

"polyplay26" wrote in message
news:50650000000800000056C30000-1077587809000@exchange.ni.com...
> when using ni-daq 6.9.3 with AT-AI-16XE-10 it works OK!.using ni-daq
> 7.1 traditional first DMA channel does not respond.help please!
What OS? Do you have a sound card?
Mohan Pawar

Multiple AXI DMA channels on zedboard

Hello All,
I am trying to use the two HP ports in zedboard by connecting axi-dma [instantiating two times] in a loopback fashion. I have already written a linux driver for single axi-dma connected to one HP port in a loopback fashion and it is working fine. Now I am extending to use multiple HP ports but could not able to do it successfully. I have also updated the device tree file with new axi-dma instantiation, created the necessary bitstream and loaded into the board.
I referred the xilinx website,
http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs
They say "NOTE: Multi-channel mode of AXI DMA is not supported in the driver."
Meaning, I cannot able to use the remaining HP ports with axi-dma driver?
Could you please give me some suggestions or websites or threads for this concern?
Thanks,
Mani...

Hello and All,
I forgot to ask one more thing.... While I was doing experiments with Xilinx axi-dma I was not able to get the interrupts working...
Well I will try to explain bit more,
Linux driver is developed using the dma generic engine with the following procedure,
i) Get the dma slave channel with proper mask and filter.
ii) prepare for the dma copy with the correct direction.
iii) Register a callback [On completion this callback should be called automatically]
iv) Submit the transaction
v) Issue the transaction....
vi) Wait for a flag until it becomes some specified value for termination... and this flag will be set to the proper value only in the callback....
If I follow this procedure, then every time my driver get hangs since there is no callback being called after completion.....
So I removed the final step and it seems everything works correctly.... I could able to see the updated and correct values....
Of course, this is not the proper way of assessing the time taken for writing data using dma.....
Any idea about this issue?
I made sure the F2P thing is enabled and also I could able to see cdma interrrupt is getting registered in /proc/interrupt....

Simultaneous I/O with DMA FIFO channels on cRio

Hy everybody,
I work on a CompactRio 9014, with NI 9263 for analog output and NI 9215 for analog input.
I want to do simultaneous acquisition and generation using DMA channels: one on the first channel for the input and the second on the second channel for the output.
I have already read the example CompactRio Simultaneous AI and AO streaming But, if in this example the Analog input is done by a DMA FIFO, the output is done using the FPGA host interface read/write node (register I/O).
In my case I try to use two DMA channels, one for transfering the input datas and the second to transmit the output datas from the RT vi to the fpga VI.
So I have configure two FIFOs, both of size of about 4000. My sampling rate (for input and output) at the level of the fpga is 20KHz. I want to output blocks of size 2000 and simultaneous read something that is directly linked to my output. The problem, (I suppose) is that I have to wait on the Invoke Node (wich read block from the Input FIFO) that the reading of the block is completed. In my application, things works well at the beginning but after some seconds the output become instable.
I think the way I program my simultaneous analog I/O is not correct, but I don't see the right way to do that with two DMA channels. I have attached my RT VI and my FPGA VI. (the probleme of I/O is in the case "faulse" in the Room_measurements VI)
I hope somebody can help me.
Thanks in advance for your answers
Attachments:
Room_measurement_RT.vi ‏339 KB
Room_measurement_FPGA.vi ‏566 KB

Hello,
I now try to separate in two timed loops the input and the output. Each of the loops run at 100ms. The first loop (generation loop) must generate a sinus during 15 seconds(So the loop must run 150 times because dt is 100ms). The second loop (input), must record an input during 30 seconds. I am also not sure if the timeouts parameters of the FIFO read/write are correct.
I think this way (see the jpg) is better. But I still have several problems:
When I launch my VI, it works at the beginning but stops after some seconds (in fact I loose the connexion)
Also, if I stop the output loop before that the input stops, the VI also stops.
I hope somebody can help me
I attache my last_VIs
Attachments:
testAOAI1.vi ‏388 KB
Room_measurement_FPGA1.vi ‏566 KB

How to transmit counter input data of different channels simultaneously?

Hello.
I'm using X-series PCIe-6361 DAQ board which have 8 DMA channels and Labview 8.2.1. I upgraded the version of DAQmx as 9.0 which supports the X-series devices and confirmed the board worked normally on my system.
I'm trying to measure the pulse width continuously from 4 different pulse trains with CMOS level. The frequencies of signals are same but the pulse width and phase are varying with respect to time.
http://zone.ni.com/devzone/cda/tut/p/id/9376
From the tutorial page of NI X-series, I saw the following expression "X Series also includes eight DMA channels to stream data directly
between the device and PC memory without CPU interaction or additional
programming effort. These eight channels provide parallel data streams for the analog I/O, digital I/O, and all four counter/timers."
But when I started the Labview programming, I realized that the counter functions of different channel cannot be put into a single task. So I couldn't help but separate the read functions into 4 individual tasks and there are timing differences in data transmission between channels up to 250 micro-sec because of the sequential running.
How can I eliminate the timing difference and realize parallel data streams for the counter?

Check out these links. I hope that they help!
Fieldpoint and RT
Logging Data with a FieldPoint FP-20xx to View in a Web Browser
Transferring Files from a FieldPoint FP-20xx through an FTP Server
Introduction to Using DataSocket Commands to Communicate with FieldPoint Etherne
t Network Modules
Good Luck!
Mike
NI

No. of Channels in a PXI Embedded Controller

How many DMA channels are present in the NI PXI 8105 controller ? I have read that in NI PXI 7831 r, there are a total of 3 DMA channels, So if I am using 3 such cards I need to have 9 DMA channels in my controller for sending the data to these cards simultaneously.

I would rank your options this way (with #1 being the least demanding on your controller's memory):
1. FTP from the PC to the controller's hard drive, copy over the data, and then delete it. This way, the PC is doing all the work, and the controller is left to just gather data and do its own processing. The catch is that your network capabilities will determine how fast you can do this. Also, you'd have to make sure you aren't deleting data the controller hasn't processed yet.
2. Store the data in Shared Variables, so that both the controller and the PC can see and use the variables in real-time as they are updated. However, lots of shared variables = very messy code.
3. TCP/IP is your last option for transferring data. It will be the most demanding on the controller since it will need to open and close ports and handshake.
With all of these, you shouldn't lose any data if it's programmed properly.
Product Support Engineer
National Instruments

Dma interrupt transfer modes in 6602

I am using four simultaneous counters of a 6602 in continuous buffer modes
using traditional DAQ. Gates used are PFI38 PFI 26 PFI 18 PFI 10.
When I use set DAQ Device Information.vi to specify the "data transfer
mode for GPCTR # " either in DMA (3 of them) or interruption mode ( one of
them), I am not sure which # to use for the GPCTR #.
In other words, must I specify GPCTR0, 3, 5 in DMA and GPCTR7 in interrupt?
Otherwise stated, the simple fact that I use predefined PFI would associate
the GPCTR concerned or, else, are these GPCTR defined as GPCTR0, 1, 2, and 3
in the order I open their configurations in my Labview program.
There is no clear definition of what GPCTR # actually mean in the Labview
references.
I have the feeling that some counters generating 15000 counts/sec do not use
DMA but interrupt transfer modes instead.
Gérard

GPCTR# is the general purpose counter resource you are using, there are eight 32-bit counters on the 6602 card. Unfortunately there are only 3DMA channels which means that if you plan on 4 very high speed buffered counting acquisitions then you could have some trouble since interrupts run much slower than the DMA channels. I have had no problem using a mix of interrupts and DMA channels for continuously buffered counting with 4-8 counters at a time but the collection rate was only a few KHz faster than this the buffering using interrupts can not keep up an will overrun causing a "buffer overrun" error. If you really need many highspeed buffer counters running simultaneously you could try using 2 cards but this seems costly (RTSI cable will allow multi-card synchronization).
Paul
Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA

Downcasting DMA data from U16 to U8

Hi Everyone,
I have a situation that I hope someone can shed some light on. Currently I have an FPGA design that collect highspeed data does some processing on it and spits out the results over DMA for the host to read out and save to TDMS files. Currently I am reading 4MB worth of I16 data from the DMA every 25-30 ms, the current design is able to keep up with the data rate just fine. My next task is to allow the FPGA to collect the same type of data, with the same processing, only providing the data back in I8 format, which means one of the following design decisions:
1- keep existing FPGA code/FW and cast the data to I8 on the host side.
The downside to the first option, is the high data rate. I did some benchmark testing with a couple of different methods to do the I16 to I8 cast (Number Split, to I8 cast, and Typecast). Needless to say the Typecast was too slow for my operations averaging about 35-40 ms to cast the 4MB worth of I16 data to I8. The number split and to I8 cast both came with an average time of approximatly 15ms but with a max time of 23 ms. These times were obtained with a system with very little load, which will not be the case on the final design.
2- develop/compile a new FPGA VI that does the exact same operations except convert the data to I8 on the FPGA and send it over a DMA defined with I8 datatype.
The downside here is the need to maintane two versions of the FPGA code as well as two versions of the driver code, this is since the DMA used to transfer the data has changed datatype from I16 to I8 which prevents me from using a dynamic refrence when operating with the FPGA. I also am using all the available DMA channels on board so I cannot just declare both I16 and I8 DMAs and read from the appropriate one on the driver side.
My question is, is there a cheap way of doing the cast operation on the host side? It was mentioned that LV FPGA will use U64 to transfer the data internally and only cast it to the required data type at the end, is it possible to leverage this operation to get it to cast to a differnt data type on the driver side, if this is true? Otherwise is there a fourth method of doing the cast that is cheaper? any other ideas are welcome.
Sorry for the long post.
Solved!
Go to Solution.

Update your FPGA to be configurable to either pack I16s or I8 into its DMA stream, that way you have one FPGA to maintain and you have a reduced stream from the I8 configured FPGAs (i.e. half the number of DMA values should be sent). Send your DMA values to always be some multiple of I16 so you can easily pack and unpack once they are in TDMS files. The host side always receives the same DMA element (e.g. I16) and doesn't really care that in some cases it contains two I8s.

Dma for dell dimension 4700 sata

Hello, I am running SJD release 2. I installed xine for wmv and dvd. The dvd plays but the video is jerky. hdparm -d1 /dev/sr0 doesn't work with "device doesn't support dma". same for the hard drive hda. In order to install and boot I have to set the bios hard drive operation (sata,pata) to "combination" or I won't see the hard drive to boot from. It will not boot with the bios drive operation setting set to "normal". I just found out from the dell site that dma will not work with the drive operation setting in "combination". The box has 8 dma channels too. Am I SOL on DMA for the dvd and hard drive with SJD on a dell dimension 4700? I saw a patch at sunsolve for dell sata devices, but the page said all the SJD patches were at the online update, so they were for solaris and I had no access to it anyways. Does anyone know of an SJD release 2 equivalent patch for this? I haven't been able to connect to the online update for the last several days, whereas a few months ago I was able to. I can get to the site to download them manually, but have no idea which one or how to search for it.

Dell's really don't mind having other hardware installed...in fact, it's actually very easy to do. In the two dells that I've owned, they both took new memory, new hard disks, and some assorted PCI cards. I'm still unsure why everyone says Dells suck with upgrading.
The fact that the problem occurred on three different computers shows me that the card is dead. I'm not surprised the card was detected on one machine, as that happened to me when my card died. Sometimes it would be detected, other times it wouldn't. Sometimes I could almost get through the driver installs, other times it wouldn't do anything.

Freeing DMA channels

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