Dma channel problems

Hello,
I really need help on this one. Using PCI-6035E I am trying to output an analog signal (actually 2 waverforms interleaved together) on 2 channels while simultaneously using the two GPCTRs to measure two separate signals' pulse widths. The VI runs perfectly on some occasions, while on others I get "no DMA channel available for use". Whenever this message appears and I try to exit labview, the nipalk.sys driver messes up and I get a blue screen crash that says "process_has_locked_pages" (I traced the locked pages to this driver). I've tested this many times and it appears to me to be totally random. I've used the Set DAQ device information VI to set the two counters to use interrupts, but I need to use the one DMA channel for
the analog output. My best guess is that there is some kind of resource conflict with something else in the PC, but I can't figure out how to change DMA assignments(I'm using Windows XP). The NI-DAQ Measurement and Automation Explorer tells me that the card is using DMA 0, IRQ 17. I've tried uninstalling all the NI-DAQ drivers, reinstalling and updating. Any help anybody could give me would be greatly appreciated.
Thanks,
Nick
Attachments:
aug7.vi ‏374 KB

Hello;
The PCI bus has 3 DMA channels that are share in between all devices that do DMA data transfers.There is nothing you can do to change that, since that is a PCI bus feature.
The best way to go about that is to remove other devices that use DMA, such as network cards, for instance. That might free up more DMA access time for your DAQ device to execute its data trasnfers.
Hope this helps.
Filipe A.
Applications Engineer
National Instruments

Similar Messages

X Series DDK: Configure Interrupt on DMA Channel's total transfer count

Hello,
In the DAQ-STC3 X Series DDK Reference Manual, Chapter 1: Theroy of Operation, Section Interrupts, Subsection Special Considerations: Maximizing Throughput in Low-Latency Situations (p41), it is said:
"for X Series devices, the CHInCh can interrupt on the DMA channel’s total transfer count, which occurs once the data has been completely transferred to the host memory. The order of programming for this situation (and output operations) is as follows:
1. Program the DMA channel’s Total_Transfer_Count_Compare_Register (CHTTCCR) with the number of Bytes in a single input/output sample.
2. Set the DMA channel’s Notify on Total Count flag in the CHCR.
3. Set the DMA channel’s Arm Total Count Interrupt flag in the CHOR.
4. Start data transfer (through the DMA controller and the subsystem’s Stream Circuit).
5. Receive total transfer count interrupt.
6. Increase the CHTTCCR by the number of Bytes in a single input/output sample.
7. Re-arm the total transfer count interrupt in the CHOR.
Using the X Series DDK, I don't manage to perform such a configuration.
Can you please provide me code sample to do so ?
Thanks in advance for your support.
Sincerely
Bertrand

Hello Steve,
Weeks ago, we developed a Linux application that configure NI acquisition board (serie X) to send an interrupt when FIFO count reach a given number. At this stage we manage to prove that our board configuration was good and that the problem was due to INtime. TenAsys (INtime developers) fix this issue few weeks ago.
We just come back from holidays, apply the modifications created by TenAsys and manage to get interrupt inside INtime.
We still have two problems.
Reading DMA
===========
From the interrupt handler, when we access to the DMA to get samples stored in the FIFO, we manage to get the samples inside the first interrupt handler. With the following interrupts, when accessing DMA with the tCHInChDMAChannel structure, it said that there is no available bytes. But when we read the Channel_Total_Transfer_Count_Status_Register from the DMA channel, we see that we have the desired numbers of samples.
In the interrupt handler, during the interrupt aknowledgement, instead of only reading the Volatile_Interrupt_Status_Register to ackowledge the interrupt, if I increase the Channel_Total_Transfer_Count_Compare_Register_LSW by a given number (X) then I got X samples to read in the following interrupt. Problem with this solution is that the delay between two interrupts is not constant.
It seems that we mis-configured the DMA channel. But don't manage to find the error.
Two interrupts generated
====================
Moreover, we always get 2 FIFO_Count interrupts. Even configuring conversion, sampling and interrupt frequencies at very low value (conversion 1KHz, sampling 1Hz, interrupt generation: 1Hz). The delay between the two interrupts is about few nano seconds.
Source code
============
I attach to this post the source code we use to play/test this configuration. There is a Visual Studio workspace that we used to play with INtime and a CMake configuration file that we used to manage our Linux tests. You can find all the informations you need to build the binary in the README file.
Thanks in advance for your help with these issues.
Sincerely
Bertrand Cachet
Attachments:
IOMonitoring.zip ‏355 KB

Number of DMA Channel on System

I need to log 16 (my be 32 later) simultaneous channel at the same time.
Is the limit of DMA chanels a windows system problem or just a card problem?
I understand that there is a limited number depending on the operating system.
So I cannot use 4 6601E cards (4 chanels each)at the same time on a PC.
I am told my NI that I could us PXI rack with a number of 6115 cards and an embeded controller running Window but I can not see that this would resolve the DMA problem unless it was a modified window system.
The other problem I see is that if Window 2000 or XP configers the cards to use he same chanel, Window will not let you change anything youself as all seeting are allway grayed out.
Judging my the large number of post on DMA perha
ps NI should write a white paper detaiing all the problems.
Thanks in advance fr your help.
Colin

Hello Colin,
Back with the ISA boards the limit of DMA channels was due to the computer itself. Now with PCI, DMA is handled by the PCI board itself. There has to be separate DMA controller hardware for each DMA channel. Our controller chip suppports up to 3 DMA channels. So I wouldn't say that this is a problem really. It's simply what the card offers, similar to the number of counters that is on the board.
There are fewer DMA channels than counters because 1) more DMA controllers would be more expensive, 2) Most applications probably would not require DMA channels for every counter. Interrupts may be sufficient for slower acquisitions or the the counters may be used for pulse generation which also wouldn't require DMA.
I guess I don't know enough abo
ut your application to comment on the 6115 suggestion. The 6115 is an analog simultaneous sampling board, but they only have 2 counters each. Perhaps it was suggested that you acquire this data with analog sampling. The advantage to this is that you can use the same DMA channel for all analog channels being scanned which would probably be a good alternative for your application.
Russell
Applications Engineer
National Instruments
http://www.ni.com/support

How many DMA Channels does my device have?

I would like to know how I can find out (progammatically) how many DMA channels my device has. I am using the DAQmx driver. Other than with the traditional DAQ I can't find out anything about my device but the "type" and the "serial number". Where can I get some more details about the device (not in the MAX - I want to know it in my program) with DAQmx?
My intention is to find out how many DMA Channels the device has and depending on how many Channels I need - I am using "interrupts" instead of DMA.
Somewhere in the KB of Ni was written that the NI-DAQ 6.9.... realizes automatically how many DMA Channels are available and how many I would need - and so he takes "interrupts" for the rest.
It seems that they did a "step bac
kwards" because with the NI-DAQ 7.2 it doesn't work automatically if I need DAQmx VI's.
Does somebody know anything that would help me to solve this problem?
Thanks.

Sorry! I posted my first revision of the answer.
Here is what I meant to say:
Hello,
According to this KnowledgeBase, DAQmx and Traditional DAQ behave the same. Are you seeing something different?
As far as a workaround goes, all you have to do is trap the No DMA error. This error should be -200251. So in software, if you receive error -200251, then you need to configure the board to use interrupts, and then start the task again.
How to configure the board for interrupts differs from the four different DAQmx API�s (C, C++, DotNET, and LabVIEW). If you are unclear about how to do this in your environment, please let us know, and we can find
out.
Best regards,
Justin T.
National Instruments

Sender JDBC Commn channel problem - Channel is not reading any data.

Hi,
I am referring to the following blog as i have exactly the same problem:
[Blog|Sender JDBC Commn channel problem;
I communication channel monitoring i am getting the following logs -
6/21/10 7:19:07 PM Processing started
6/21/10 7:19:07 PM Retry interval started. Length: 86400.0 seconds
Here in the channel the poling interval is 86400 seconds.
Now according to this blog the solution to my issue is "Check whether anything is locked in "Locking adapter" in VA? If there is then just release the lock and restart the comm channel. Note: In "locking adapter" the name will be something like $XIDBAD.JDBC2XI."
Mine is a PI7.1 system and i am not able to find any thing like this in NWA.
Can some one please help me on this?
Thanks & Regards,
Anshul

try;
Goto NWA -> Availability and Performance Management -> Resource Monitoring -> Locks

Freeing DMA channels

I am using pattern gen. single buf. input on a 6533 with Win2k and Borland C++ v5. When the program using the board (via NI-DAQ, the latest version) dies badly, it does not seem to free the DMA channel that the board is using. I get the "No DMA channel available for use" error when I run my program again. This means that I have to reboot.
How can I free the DMA channel used by the 6533 without rebooting? I have tried to use DIG_Block_Clear at the start of my program, but it complains that no transfer is in progress.

DAQ_Clear is for DAQ devices, not DIO devices. I get an error -10403 "Device does not support the requested action" when I try this function.
BTW: I mistankenly said I had a 6533; I actually have a PCI-DIO-32HS (they are pretty much the same thing, the 32HS uses PCI instead of PXI).

Finite Measure with 2 boards 6602 and 6 DMA Channel Counter Buffered - error 200141

Hi all,
First .. I'm a beginner with LabView and I hope to explane myself in good way cause I'm italian..
I red all the post about the error 200141 and check the suggested solutions (also the way to ignore the error), but I want try to ask for a differet one..
What i'm trying to do is to aquire 6 encoder, 3 on the first board PCI 6602 and 3 encoder on the second board on DMA channels.
The encoder generate 90000 X4 = 360000 pulses x revolution and the max speed rotaion is 4 RPs.
Cause I need to store in a bin file all the pulses from the encoders, i generate a trigger of 1.5 MHz to get all the samples at the max system speed (360000 * 4 = 1440000 pulses x sec).
I think to have reached the limit, and maybe is not possible do better.. actually the 2 PCI 6602 works with 1,0 MHz of trigger and the system store in 6 files 4000000 of samples during
the finite measure of the angular position on 6 channels.
The trigger is not yet sync between the 2 PCI cause I'm waiting for a RTSI cable to put in the PC...
In Your opinion is possible to find a alternative way to acquire these encoders ?..
Thanks

I also doubt if you need to capture every single increment from each encoder. I'll discuss this more below.
Further, many earlier discussions suggest that counter tasks can sustain data transfers merely in the 100's of kHz, with *maybe* a possibility under special circumstances to slightly exceed 1 MHz. Your boards have very small hardware buffers (either 1 or 2 samples worth), causing the PCI bus usage to be very frequent and therefore less efficient.
Now, let's go back to your sample rate. You've got encoders which suggests that you're dealing with a physical system. Physical systems have inertia, which limits their useful bandwidth. In my experience, it's quite unusual to care about motion artifacts beyond the 10's of kHz. The inertia just doesn't allow anything significant to happen at that rate.
So, if the physical bandwidth of your motion system is, say, 5 kHz, there's a rule of thumb suggesting to measure at 10x when possible. So that'd mean 50 kHz sampling. 50 kHz x 6 channels on the PCI bus may be possible. Multi-MHz sampling won't be.
Can you describe the physical system a bit?
-Kevin P.

Number of DMA channels

如題，
我手邊有9636/9633兩張卡，
手冊上都是寫Number of DMA channels=5
請問這個數量跟FIFO Target to host DMA是一樣的意思嗎?
因為我設超過3個FIFO Target to host DMA，就會出現錯誤。
還有FPGA的FIFO最大個數是多少?
因為設3個FIFO Target to host DMA+2個FIFO Target scoped
有時候可以過，有時不行，有時程式還會閃退，真是OOXX
附件:
2013-05-30_151309.jpg ‏45 KB

http://www.ni.com/pdf/manuals/372596b.pdf
Number of DMA channels
http://digital.ni.com/public.nsf/allkb/22E2CE79F77B27508625794C00188265
http://digital.ni.com/public.nsf/allkb/470FF5EE8FD677F58625760A007562B9
您的應用為何?

Using ni-daq 7.1 traditional for AT-AI-16XE-10 first DMA channel doesn't respond

when using ni-daq 6.9.3 with AT-AI-16XE-10 it works OK!.using ni-daq 7.1 traditional first DMA channel does not respond.help please!

"polyplay26" wrote in message
news:50650000000800000056C30000-1077587809000@exchange.ni.com...
> when using ni-daq 6.9.3 with AT-AI-16XE-10 it works OK!.using ni-daq
> 7.1 traditional first DMA channel does not respond.help please!
What OS? Do you have a sound card?
Mohan Pawar

MSI BIG BANG TRINERGY dual channel problem!

Hey forum, I just installed a newly bought msi big bang trinergy. Everything went according to plan except from the point where I installed the 4gb (2x2gb) ram dimms( I have the XMS3, 4gb kit by Corsair).
Let it be noted that i followed the instruction manual and installed the dimms in the proper slots. Then when the moment of truth came and powered up my pc, it wouldnt boot. It would go into an endless restart cycle without booting. Then i unplugged the dimm3 and started only using dimm1 and everything went well. I also switched the ram dimms (in case one of them was faulty) and placed it in dimm1 and again there was no problem.
My take on this situation is that there must be some hardware problem concerning DIMM3. I also run a BIOS update in hopes that something might change but no luck.
..So what is your take on this?
Thank you in advance for the advice.
P.S Since i had a P55 mobo before Big bang i read that format is not necessary so i didnt format the pc. Can that be the cause of the dual channel mal-function?

Quote from: Jack on 11-May-11, 22:57:43
Nope.
There are a couple of explanations for the behaviour:
1) there is a problem with the modules
2) the memory slot itself or underlying circuits is/are defective
3) there is a short circuit problem somewhere inside the case which basically blocks that particular memory slot
4) the CPU (or its memory controller) is defective
5) there is some sort of pin-contact problem [bad contacts between the board's socket pins and the contact pads of the processor], caused by bent or broken pins or by too much pressure exerted by the CPU's heatsink
I would start poking at explanation 3) by testing the board outside the case on a non-conducting surface in barebone configuration and, in case that does not change anything, go for number 5): take off the heatsink and inspect both socket pins and contact pads for any irregularities [use a magnifying glass!]
I went to a technician to check the mobo where we tried different memory modules and cpu (100% working ) on a bench table.The pins on the mobo were not bent or anything. We checked all the points you mentioned that needed to be checked but still the problem persisted so it was a memory slot problem. Thanks for all the help! Really appreciate it, the replaced mobo works perfectly

Dual channel problems?

Hi all, I purchased an 8GB set of 10666 GSkill memory for my dv7t-3300 CTO core i7 laptop in December of last year. I first posted in the G.Skill support forums and they recommended I try HP, I will copy over my entire post there as it is detailed as to what I did last week.
Hi all, I've been having some weird issues that I can't be sure are memory related. It's lengthy but I'm trying to explain what all I did and why it's so confusing.
Last December I bought an 8GB memory set for my HP dv7t Quad (Core i7 720QM) laptop, the memory model is F3-10666CL9D-8GBSQ. Shortly after installing them I started to get a random BSOD for MEMORY_MANAGEMENT, but it is so rare and usually happens when I am away from the computer. The past month or so I have also been having my web browser random close quite often, sometimes 5 times in an hour (I use Palemoon/Firefox and it is constantly using over 500MB).
This week was dedicated to memory tests, I ran memtest86+ almost every evening in various configurations. I started with how it had been set up for months and I managed to get some errors in test 5 that were around 2000MB and 3000MB. The next step was to run each stick individually... no errors after 10 hours on each stick. I then put them both back in and ran the test again, no errors again. I then switched the sticks around and ran again, got errors in the same spots. I also tried using the standard memtest86 and the Windows Memory Diagnostic available on the Ultimate Boot CD, neither of which showed any errors at all with both sticks in. I also found MemTest 4.0 from HCI Designs that runs within windows, and it found an error in one of the 3 sessions but did not say where it was.
I have since put my original sticks into the laptop which were 1 2GB and 1 1GB stick from Samsung. Thus far (less than 12 hours) I have not had a single random browser close and no BSOD. I am wondering if the problem is the sticks themselves or dual channel being used(I assume dual channel only works if both sticks are the same size). I looked in the BIOS and can't find a way to disable dual channel, or any advanced BIOS options at all, and I do have the most recent BIOS from HP.
Does anyone have any opinions as to what I can try before trying a new set of memory? If it is related to the dual channel I'll just live with it and get mismatched sticks, not going to send it in under warranty for something easily by-passable.
One of the site admins over there was wodnering if there was any sort of BIOS upgrade planned in the near future. I'm not expecting anything since the last update released by HP was in December of 2010. If there is nothing else that can be done I will just live without dual channel as the memory appears to be working. As I mentioned in the other thread, this is something too small to be without a PC for warranty work.

Read here https://forum-en.msi.com/index.php?topic=117284.msg883658#msg883658

M-Series Buffered Event Counting with DMA -- gating problem

Hi --
I am implementing DMA-based buffered event counting on a PCIe-6259 board. I use G0_Out as the gate for G1, which counts events on a PFI pin. So by setting the speed of G0, I get an event count (either cumulative or non-cumulative) on a periodic basis, which is directly DMA'd to my buffer, and synchronized with other i/o operations.
This is working well right now, except for one problem, which is that the I only get data if there is at least one source edge between gates. i.e. if there are no edges, nothing gets pumped to the dma buffer.
I am guessing that a stale data error is somehow choking off the DMA transfer from the counter. Is that possible?
Is there some magic that I need to do to avoid this, because for this application, especially if I am counting cumulatively, I don't care about a missing edge, but I do care if the dma transfers get out of phase with the rest of my timing.
Thanks in advance for any help!
--spg
Here is a snippet of the code that sets up the event counting on G1, partly based on gpctex6.cpp:
const int sDMASelect[] = {1,2,4,8,3,5};
// source: pfi, or -1 for 20Khz clock
void eventTimerSetup(tMSeries *board, tTIO *tio, int dmaChannel, bool cumulative, int source)
   int sourceSelect = (source==-1) ? 0 : (source+1);
   //MSeries.CTR.Source
   tio->G1_Input_Select.setG1_Source_Select(sourceSelect); // (pfi+1) or 20Khz=0
   tio->G1_Input_Select.setG1_Source_Polarity(0); //rising=0
   tio->G1_Input_Select.setG1_OR_Gate(0);
   tio->G1_Input_Select.flush();
   //MSeries.CTR.Gate
   tio->G1_Input_Select.setG1_Gate_Select(20); //the G_OUT signal from other clock=20
   tio->G1_Input_Select.setG1_Output_Polarity(0); //active high=0
   tio->G1_Input_Select.flush();
   //MSeries.CTR.IncrementRegisters
   tio->G1_AutoIncrement.writeRegister(0);
   //MSeries.CTR.InitialCountRegisters
   tio->G1_Mode.writeG1_Load_Source_Select(tTIO::tG1_Mode::kG1_Load_Source_SelectLoad_A);
   tio->G1_Load_A.writeRegister(0);
   tio->G1_Command.writeG1_Load(1);
   tio->G1_Load_B.writeRegister(0);
   tio->G1_Load_A.writeRegister(0);
   tio->G1_Command.setG1_Bank_Switch_Enable(tTIO::tG1_Command::kG1_Bank_Switch_EnableBank_X);
   tio->G1_Command.setG1_Bank_Switch_Mode(tTIO::tG1_Command::kG1_Bank_Switch_ModeGate);
   tio->G1_Command.flush();
   //MSeries.CTR.ApplicationRegisters
   tio->G1_Input_Select.setG1_Gate_Select_Load_Source(0);
   tio->G1_Mode.setG1_Reload_Source_Switching(tTIO::tG1_Mode::kG1_Reload_Source_SwitchingAlternate);
   tio->G1_Mode.setG1_Loading_On_Gate(cumulative ? tTIO::tG1_Mode::kG1_Loading_On_GateNo_Reload : tTIO::tG1_Mode::kG1_Loading_On_GateReload_On_Stop_Gate);
   tio->G1_Mode.setG1_Loading_On_TC(tTIO::tG1_Mode::kG1_Loading_On_TCRollover_On_TC);
   tio->G1_Mode.setG1_Gating_Mode (tTIO::tG1_Mode::kG1_Gating_ModeEdge_Gating_Active_High);
   tio->G1_Mode.setG1_Gate_On_Both_Edges (tTIO::tG1_Mode::kG1_Gate_On_Both_EdgesBoth_Edges_Disabled);
   tio->G1_Mode.setG1_Trigger_Mode_For_Edge_Gate(tTIO::tG1_Mode::kG1_Trigger_Mode_For_Edge_GateGate_Does_Not_Stop);
   tio->G1_Mode.setG1_Stop_Mode(tTIO::tG1_Mode::kG1_Stop_ModeStop_On_Gate);
   tio->G1_Mode.setG1_Counting_Once(tTIO::tG1_Mode::kG1_Counting_OnceNo_HW_Disarm);
   tio->G1_Second_Gate.setG1_Second_Gate_Gating_Mode(0);
   tio->G1_Input_Select.flush();
   tio->G1_Mode.flush();
   tio->G1_Second_Gate.flush();
   //MSeries.CTR.UpDown.Registers
   tio->G1_Command.writeG1_Up_Down(tTIO::tG1_Command::kG1_Up_DownSoftware_Up); //kG1_Up_DownSoftware_Down
   //MSeries.CTR.OutputRegisters
   tio->G1_Mode.writeG1_Output_Mode(tTIO::tG1_Mode::kG1_Output_ModePulse);
   tio->G1_Input_Select.writeG1_Output_Polarity(0);
   //MSeries.CTR.BufferEnable
   board->G1_DMA_Config.writeG1_DMA_Reset(1);
   board->G1_DMA_Config.setG1_DMA_Write(0);
   board->G1_DMA_Config.setG1_DMA_Int_Enable(0);
   board->G1_DMA_Config.setG1_DMA_Enable(1);
   board->G1_DMA_Config.flush();
   tio->G1_Counting_Mode.setG1_Encoder_Counting_Mode(0);
   tio->G1_Counting_Mode.setG1_Alternate_Synchronization(0);
   tio->G1_Counting_Mode.flush();
   //MSeries.CTR.EnableOutput
   //board->Analog_Trigger_Etc.setGPFO_1_Output_Enable(tMSeries::tAnalog_Trigger_Etc::kGPFO_1_Output_EnableOutput);
   //board->Analog_Trigger_Etc.setGPFO_1_Output_Select(tMSeries::tAnalog_Trigger_Etc::kGPFO_1_Output_SelectG_OUT);
   //board->Analog_Trigger_Etc.flush();
   //MSeries.CTR.StartTriggerRegisters
   tio->G1_MSeries_Counting_Mode.writeG1_MSeries_HW_Arm_Enable(0);
   board->G0_G1_Select.writeG1_DMA_Select(sDMASelect[dmaChannel]);
   tio->G1_Command.writeG1_Arm(1); // arm it
Scott Gillespie
http://www.appliedbrain.com
scott gillespie
applied brain, inc.
Solved!
Go to Solution.

Okay, I have it working now. In addition to your suggested changes, I had to remove the following line:
tio->G1_MSeries_Counting_Mode.writeG1_MSeries_HW_Arm_Enable(0);
It appears that writing something to MSeries_Counting_Mode causes that register to supersede the Counting_Mode register. Is that right?
So code that now works for me is listed below.
thanks Tom!
-spg
void eventCounterSetup(tMSeries *board, tTIO *tio, int dmaChannel, bool cumulative, int source) // pfi, or -1 for 20Khz clock
int sourceSelect = (source==-1) ? 0 : (source+1);
//MSeries.CTR.Source
tio->G1_Input_Select.setG1_Source_Select(sourceSelect); // (pfi+1) or 20Khz=0
tio->G1_Input_Select.setG1_Source_Polarity(0); //rising=0
tio->G1_Input_Select.setG1_OR_Gate(0);
tio->G1_Input_Select.flush();
//MSeries.CTR.Gate
tio->G1_Input_Select.setG1_Gate_Select(20); //the G_OUT signal from other clock=20
tio->G1_Input_Select.setG1_Output_Polarity(0); //active high=0
tio->G1_Input_Select.flush();
//MSeries.CTR.IncrementRegisters
tio->G1_AutoIncrement.writeRegister(0);
//MSeries.CTR.InitialCountRegisters
tio->G1_Mode.writeG1_Load_Source_Select(tTIO::tG1_Mode::kG1_Load_Source_SelectLoad_A);
tio->G1_Load_A.writeRegister(0);
tio->G1_Command.writeG1_Load(1);
tio->G1_Load_B.writeRegister(0);
tio->G1_Load_A.writeRegister(0);
tio->G1_Command.setG1_Bank_Switch_Enable(tTIO::tG1_Command::kG1_Bank_Switch_EnableBank_X);
tio->G1_Command.setG1_Bank_Switch_Mode(tTIO::tG1_Command::kG1_Bank_Switch_ModeGate);
tio->G1_Command.flush();
//MSeries.CTR.ApplicationRegisters
tio->G1_Input_Select.setG1_Gate_Select_Load_Source(0);
tio->G1_Mode.setG1_Reload_Source_Switching(tTIO::tG1_Mode::kG1_Reload_Source_SwitchingAlternate);
tio->G1_Mode.setG1_Loading_On_Gate(cumulative ? tTIO::tG1_Mode::kG1_Loading_On_GateNo_Reload : tTIO::tG1_Mode::kG1_Loading_On_GateReload_On_Stop_Gate);
tio->G1_Mode.setG1_Loading_On_TC(tTIO::tG1_Mode::kG1_Loading_On_TCRollover_On_TC);
tio->G1_Mode.setG1_Gating_Mode (tTIO::tG1_Mode::kG1_Gating_ModeEdge_Gating_Active_High);
tio->G1_Mode.setG1_Gate_On_Both_Edges (tTIO::tG1_Mode::kG1_Gate_On_Both_EdgesBoth_Edges_Disabled);
tio->G1_Mode.setG1_Trigger_Mode_For_Edge_Gate(tTIO::tG1_Mode::kG1_Trigger_Mode_For_Edge_GateGate_Does_Not_Stop);
tio->G1_Mode.setG1_Stop_Mode(tTIO::tG1_Mode::kG1_Stop_ModeStop_On_Gate);
tio->G1_Mode.setG1_Counting_Once(tTIO::tG1_Mode::kG1_Counting_OnceNo_HW_Disarm);
tio->G1_Second_Gate.setG1_Second_Gate_Gating_Mode(0);
tio->G1_Input_Select.flush();
tio->G1_Mode.flush();
tio->G1_Second_Gate.flush();
//MSeries.CTR.UpDown.Registers
tio->G1_Command.writeG1_Up_Down(tTIO::tG1_Command::kG1_Up_DownSoftware_Up); //kG1_Up_DownSoftware_Down
//MSeries.CTR.OutputRegisters
tio->G1_Mode.writeG1_Output_Mode(tTIO::tG1_Mode::kG1_Output_ModePulse);
tio->G1_Input_Select.writeG1_Output_Polarity(0);
//MSeries.CTR.BufferEnable
board->G1_DMA_Config.writeG1_DMA_Reset(1);
board->G1_DMA_Config.setG1_DMA_Write(0);
board->G1_DMA_Config.setG1_DMA_Int_Enable(0);
board->G1_DMA_Config.setG1_DMA_Enable(1);
board->G1_DMA_Config.flush();
// from Tom:
// The "magic" you need is referred to as synchronous counting mode (or Duplicate Count Prevention in NI-DAQmx).
// Try setting G1_Encoder_Counting_Mode to 6 (synchronous source mode) and G1_Alternate_Synchronization to 1 (enabled).
tio->G1_Counting_Mode.setG1_Encoder_Counting_Mode(6); // 0
tio->G1_Counting_Mode.setG1_Alternate_Synchronization(1); // 0
tio->G1_Counting_Mode.flush();
board->G0_G1_Select.writeG1_DMA_Select(sDMASelect[dmaChannel]);
tio->G1_Command.writeG1_Arm(1); // arm it
scott gillespie
applied brain, inc.

Memory and dual channel problems

Hi
Can someone help me?
1- I have 2x512 MB DDR 400 Twinmos CL 2.5 and amd xp 2600 (fsb 333) and Msi K7n2 delta L. I have tested separatly my sticks, one of them woks great, if i put dram clock at 166 or 200 the sytem is always stable. The other stick is not so great , if i put him at 200, most of times the sytem doesn´t boot and the lights in the d-bracket display memory problems, when it manages to boot, when i get to windows i´m always getting blue screens with error messages. If i put to 166 it´s more stable, but sometimes hapens the same, but less frequently.
I have run memtest, but it shows no errors in both sticks.
2- When i use both sticks together in dual channel dimm 1 & dimm 3 sometimes windows only displays 512 MB, but if i reboot the sytem, i get 1 GB as it should be.
It is not frequently, but sometimes it hapens.
3- How can i detect dual ddr is working or not?
I´m asking this becouse the two sticks i have are similar, but there is a little diference, one of them has twinmos chips and the other has M.tec chips. But both are from Twinmos. Sisoftware sandra shows them as equal.
I have heard that this mobo, on the boot screen should display something like this:
Memory Mode: Dual Channel
or
Memory Mode: Single Channel
But in the boot screen it only says DDR 400 or DDR 333 acording to the setings i have put in the bios.
My bios version is 5.1 (4/18/2003). Do you think i need to flash the bios?
Thanks
Pedro Cascão

Sorry, i forgot to post my bios settings.
CPU fsb clock 166 mhz
cpu interface normal
fsb/dram ratio 1:1
current dram clock 166 mhz
memory timings:
t (ras) 8
t (rcd) 3
t (rp) 3
cas latency 2.5
agp voltage 1.5 v
dram voltage 2.7 v

IDE Channel Problem?

Some background...my computer went down because the motherboard went out. I installed a new one and it was DOA...so I went with an MSI 865PE Neo2-PFS (Platinum Edition). I got it up and running and everything is great except I get the following...
Currently, I have 2 HD's on the main IDE channel, 1 DVD-RW and 1 DVD-Rom on IDE channel 2. I have a third IDE HD with an SATA converter on it hooked up to my SATA 1 port. It registers fine and I can access all of the data. I just keep getting this error. When I disable it in the Device Manager, my "SATA" drive goes away.
By the way, I use the computer for music recording. I don't want to hook my HD up as a slave to an optical as this could cause problems. This config worked fine on my other mobo.
Any help is appreciated.
Windows XP Pro w/SP2
Intel P4 3.0Ghz w/HT
2GB Kingston Hyper X RAM

Quote from: Maesus on 04-March-06, 01:15:46
Is your WinXP newly installed with this motherboard?
It could be the SATA converter you probably need a better driver for it. Can you tell more about this SATA converter that you have?
No, it is the same installation that was on the drive prior to the new motherboard. Could I simply re-install the OS and clear this problem up without having to reformat the drive?
Oh, and here's the URL for the exact SATA converter I have.
http://www.newegg.com/Product/Product.asp?Item=N82E16812107112

Photoshop CS6 spot channel problems

When I save a file created in Photoshop CS6 that has SPOT color channels it is converting the SPOT color channels to ALPHA channels when my customers are opening them into an older version of Photoshop. This has never been a problem with earlier versions of Photoshop.
Has anyone else had this problem and is there a solution?
I don't know if it is a bug in CS6 or it is a setting or something I am not finding. I have never had to set anything before this version and I have been through anything I could think of to try & discover something, but no luck.
Any help would be really appreciated as this can't keep happening. I have had to be on the phone walking them through the steps to convert the ALPHA channels back to SPOT channels but do not have the time nor should I expect my customer to have to do it.
Running Windows 7
Help please!- Thank you

I'm having the same issues and it seems this just started happening after the most recent update because this wasn't happening for the last couple months I've had CS6. Not only that I actually lost 4 hours of work after it didn't save the spot channels at all and just saved the original image (it's technically supposed to be impossible to do this without making a copy). On top of that now when my clients try to open my PSD files in previous versions it says they do not have the correct color books even though I'm not using spot colors (this did not happen before the update. I've sent several files in the past couple weeks). I'm not sure what they did recently but it really screwed things up.
I'd like to know if anyone has a work around for the color book problem short of asking my clients to buy and install the new color books. I'm having to send the spots as EPS DCS files, so they can open it. It's always a headache when you upgrade and none of your clients do. Why can't they make this stuff work backwards?

Dma channel problems

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