Multiple AXI DMA channels on zedboard

Hello All,
I am trying to use the two HP ports in zedboard by connecting axi-dma [instantiating two times] in a loopback fashion. I have already written a linux driver for single axi-dma connected to one HP port in a loopback fashion and it is working fine. Now I am extending to use multiple HP ports but could not able to do it successfully. I have also updated the device tree file with new axi-dma instantiation, created the necessary bitstream and loaded into the board.
I referred the xilinx website,
http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs
They say "NOTE: Multi-channel mode of AXI DMA is not supported in the driver."
Meaning, I cannot able to use the remaining HP ports with axi-dma driver?
Could you please give me some suggestions or websites or threads for this concern?
Thanks,
Mani...

Hello and All,
I forgot to ask one more thing.... While I was doing experiments with Xilinx axi-dma I was not able to get the interrupts working...
Well I will try to explain bit more,
Linux driver is developed using the dma generic engine with the following procedure,
i) Get the dma slave channel with proper mask and filter.
ii) prepare for the dma copy with the correct direction.
iii) Register a callback [On completion this callback should be called automatically]
iv) Submit the transaction
v) Issue the transaction....
vi) Wait for a flag until it becomes some specified value for termination... and this flag will be set to the proper value only in the callback....
If I follow this procedure, then every time my driver get hangs since there is no callback being called after completion.....
So I removed the final step and it seems everything works correctly.... I could able to see the updated and correct values....
Of course, this is not the proper way of assessing the time taken for writing data using dma.....
Any idea about this issue?
I made sure the F2P thing is enabled and also I could able to see cdma interrrupt is getting registered in /proc/interrupt....

Similar Messages

Axi DMA correct parameters

I'm making my design with Vivado HLs and Vivado and I'm doing some somewhat big transfers between DDR and my custom IP block and vice-versa.
Each transfer from DDR to custom IP is of 256x256x4=262144 bytes and it happens 4 times.
My MM2S (Memory Mapped to Stream) velocity is at 350Mbytes/s and by S2MM is at 200 Mbytes/s.
I know I can get better velocities and I guess these slow ones are related to the parameters of the Axi DMA block.
That's what I came here to ask you, to help me understand which should be the correct parameters since I still can't understand it from reading the logicore product guide.
Width of buffer length n
From what I understand this is the maximum length of the transfer in bytes like so 2^n. So in my case as 2^18=262144 shall I put 18 in here?
Memory Map Data Width
Data width in bits of the AXI MM2S Memory Map Read data bus. I have no idea here. My words have 32 bits and I defined the entrance stream of my block to have a length of 32 bits but what is this?
Stream Data Width
I guess here I should put 32 correct?
Max Burst Size
Burst partition granularity setting. This setting specifies the maximum size of the burst cycles on the AXI4-Memory Map side of MM2S. Valid values are 2, 4, 8,16, 32, 64, 128, and 256.
Again, I have no idea what to put here.
I could do a trial-and-error approach and change parameters until I find the best ones but the problem is that each re-synthesyze and re-implementation in Vivado takes a lot of time...

Hi,
The meaning of those parameters is rather simple, however it may be difficult to understand from the documentation:
Width of buffer length register - Length of internal counter / register in the DMA which stores the length of DMA operation data. It should be in your case at least 19 bits as 2^18 give you max length 262143 bytes which is lower than the requested length 262144. This parameter does not directly impact performance. It mainly impact maximal achievable frequency and has slight impact on utilized FPGA resources.
Memory Map Data Width - This specifies data-width of AXI4 interface, data width 64 bits when connected to HP or ACP port can significantly improve throughput (when connected to 64bit AXI Stream). This parameter is independent on the AXI stream data width. With 32 bit AXI Stream the improvement will be insignificant in your case. Setting this parameter to 64 has impact on utilized FPGA resources.
Stream Data Width - Width of AXI Stream interface. Set 32 here, if your component has 32 bit AXI Stream Interface.
Max Burst Size - Data on AXI interface can be transferred in bursts - N words can be transferred in one transaction on AXI. Higher burst size leads to better throughput. This parameter should be set to at least 16. You can set in to 256 (Maximum allowed by AXI4), however speedup against 16 will be small. It is caused by the fact that PS AXI interfaces are AXI3 compliant, which limits the burst size to 16. Therefore the AXI interconnect must split the AXI4 burst to several AXI3 bursts.
To improve throughput you can use:
Higher design clock frequency.
Scatter-Gather DMA to improve throughput by hiding latencies of direct register mode by utilization of multiple buffer descriptors.
64 bit AXI Stream interface in your component.
VK

Dma channel problems

Hello,
I really need help on this one. Using PCI-6035E I am trying to output an analog signal (actually 2 waverforms interleaved together) on 2 channels while simultaneously using the two GPCTRs to measure two separate signals' pulse widths. The VI runs perfectly on some occasions, while on others I get "no DMA channel available for use". Whenever this message appears and I try to exit labview, the nipalk.sys driver messes up and I get a blue screen crash that says "process_has_locked_pages" (I traced the locked pages to this driver). I've tested this many times and it appears to me to be totally random. I've used the Set DAQ device information VI to set the two counters to use interrupts, but I need to use the one DMA channel for
the analog output. My best guess is that there is some kind of resource conflict with something else in the PC, but I can't figure out how to change DMA assignments(I'm using Windows XP). The NI-DAQ Measurement and Automation Explorer tells me that the card is using DMA 0, IRQ 17. I've tried uninstalling all the NI-DAQ drivers, reinstalling and updating. Any help anybody could give me would be greatly appreciated.
Thanks,
Nick
Attachments:
aug7.vi ‏374 KB

Hello;
The PCI bus has 3 DMA channels that are share in between all devices that do DMA data transfers.There is nothing you can do to change that, since that is a PCI bus feature.
The best way to go about that is to remove other devices that use DMA, such as network cards, for instance. That might free up more DMA access time for your DAQ device to execute its data trasnfers.
Hope this helps.
Filipe A.
Applications Engineer
National Instruments

Change labels of multiple axis in xy-chart

Hi,
I want to programmatically change the labels of the axes in a xy-chart with two y-axes.
I can easily manage this for the x-axis and the first y-axis. But I can't find how to access the properties of the second y-axis. How to do this?
Steven
LV 7.1 - 8.2

There is a property named "Active Y Scale".
In dictates which of the multiple axis you are going to act on.
Set it to the index of the axis you want to change BEFORE setting the label.
Ben
Ben Rayner
I am currently active on.. MainStream Preppers
Rayner's Ridge is under construction

X Series DDK: Configure Interrupt on DMA Channel's total transfer count

Hello,
In the DAQ-STC3 X Series DDK Reference Manual, Chapter 1: Theroy of Operation, Section Interrupts, Subsection Special Considerations: Maximizing Throughput in Low-Latency Situations (p41), it is said:
"for X Series devices, the CHInCh can interrupt on the DMA channel’s total transfer count, which occurs once the data has been completely transferred to the host memory. The order of programming for this situation (and output operations) is as follows:
1. Program the DMA channel’s Total_Transfer_Count_Compare_Register (CHTTCCR) with the number of Bytes in a single input/output sample.
2. Set the DMA channel’s Notify on Total Count flag in the CHCR.
3. Set the DMA channel’s Arm Total Count Interrupt flag in the CHOR.
4. Start data transfer (through the DMA controller and the subsystem’s Stream Circuit).
5. Receive total transfer count interrupt.
6. Increase the CHTTCCR by the number of Bytes in a single input/output sample.
7. Re-arm the total transfer count interrupt in the CHOR.
Using the X Series DDK, I don't manage to perform such a configuration.
Can you please provide me code sample to do so ?
Thanks in advance for your support.
Sincerely
Bertrand

Hello Steve,
Weeks ago, we developed a Linux application that configure NI acquisition board (serie X) to send an interrupt when FIFO count reach a given number. At this stage we manage to prove that our board configuration was good and that the problem was due to INtime. TenAsys (INtime developers) fix this issue few weeks ago.
We just come back from holidays, apply the modifications created by TenAsys and manage to get interrupt inside INtime.
We still have two problems.
Reading DMA
===========
From the interrupt handler, when we access to the DMA to get samples stored in the FIFO, we manage to get the samples inside the first interrupt handler. With the following interrupts, when accessing DMA with the tCHInChDMAChannel structure, it said that there is no available bytes. But when we read the Channel_Total_Transfer_Count_Status_Register from the DMA channel, we see that we have the desired numbers of samples.
In the interrupt handler, during the interrupt aknowledgement, instead of only reading the Volatile_Interrupt_Status_Register to ackowledge the interrupt, if I increase the Channel_Total_Transfer_Count_Compare_Register_LSW by a given number (X) then I got X samples to read in the following interrupt. Problem with this solution is that the delay between two interrupts is not constant.
It seems that we mis-configured the DMA channel. But don't manage to find the error.
Two interrupts generated
====================
Moreover, we always get 2 FIFO_Count interrupts. Even configuring conversion, sampling and interrupt frequencies at very low value (conversion 1KHz, sampling 1Hz, interrupt generation: 1Hz). The delay between the two interrupts is about few nano seconds.
Source code
============
I attach to this post the source code we use to play/test this configuration. There is a Visual Studio workspace that we used to play with INtime and a CMake configuration file that we used to manage our Linux tests. You can find all the informations you need to build the binary in the README file.
Thanks in advance for your help with these issues.
Sincerely
Bertrand Cachet
Attachments:
IOMonitoring.zip ‏355 KB

Freeing DMA channels

I am using pattern gen. single buf. input on a 6533 with Win2k and Borland C++ v5. When the program using the board (via NI-DAQ, the latest version) dies badly, it does not seem to free the DMA channel that the board is using. I get the "No DMA channel available for use" error when I run my program again. This means that I have to reboot.
How can I free the DMA channel used by the 6533 without rebooting? I have tried to use DIG_Block_Clear at the start of my program, but it complains that no transfer is in progress.

DAQ_Clear is for DAQ devices, not DIO devices. I get an error -10403 "Device does not support the requested action" when I try this function.
BTW: I mistankenly said I had a 6533; I actually have a PCI-DIO-32HS (they are pretty much the same thing, the 32HS uses PCI instead of PXI).

Finite Measure with 2 boards 6602 and 6 DMA Channel Counter Buffered - error 200141

Hi all,
First .. I'm a beginner with LabView and I hope to explane myself in good way cause I'm italian..
I red all the post about the error 200141 and check the suggested solutions (also the way to ignore the error), but I want try to ask for a differet one..
What i'm trying to do is to aquire 6 encoder, 3 on the first board PCI 6602 and 3 encoder on the second board on DMA channels.
The encoder generate 90000 X4 = 360000 pulses x revolution and the max speed rotaion is 4 RPs.
Cause I need to store in a bin file all the pulses from the encoders, i generate a trigger of 1.5 MHz to get all the samples at the max system speed (360000 * 4 = 1440000 pulses x sec).
I think to have reached the limit, and maybe is not possible do better.. actually the 2 PCI 6602 works with 1,0 MHz of trigger and the system store in 6 files 4000000 of samples during
the finite measure of the angular position on 6 channels.
The trigger is not yet sync between the 2 PCI cause I'm waiting for a RTSI cable to put in the PC...
In Your opinion is possible to find a alternative way to acquire these encoders ?..
Thanks

I also doubt if you need to capture every single increment from each encoder. I'll discuss this more below.
Further, many earlier discussions suggest that counter tasks can sustain data transfers merely in the 100's of kHz, with *maybe* a possibility under special circumstances to slightly exceed 1 MHz. Your boards have very small hardware buffers (either 1 or 2 samples worth), causing the PCI bus usage to be very frequent and therefore less efficient.
Now, let's go back to your sample rate. You've got encoders which suggests that you're dealing with a physical system. Physical systems have inertia, which limits their useful bandwidth. In my experience, it's quite unusual to care about motion artifacts beyond the 10's of kHz. The inertia just doesn't allow anything significant to happen at that rate.
So, if the physical bandwidth of your motion system is, say, 5 kHz, there's a rule of thumb suggesting to measure at 10x when possible. So that'd mean 50 kHz sampling. 50 kHz x 6 channels on the PCI bus may be possible. Multi-MHz sampling won't be.
Can you describe the physical system a bit?
-Kevin P.

Compiling AXI DMA linux drivers in SDK.

Hi guys,
I think I'm doing something wrong and It's making me crazy. I've got:
Vivado 2015.2 w/ SDK.
Zynq zc702.
Tested in Linux 14.04 and Windows 7.
And I want to use the axi dma drivers in a Linux application so that I downloaded the axidma_test.c example. At first most of the linux libraries threw an error until I linked somehow the libraries I found in the git repository "linux-xlnx/include".
Then all of the "linux/*.h" libraries are recognized, but a new error appears: fatal error: asm/linkage.h not found. I tried to include this last one but I just made it worse. I cut down the code so that I only have a small snippet, having the same error:
#include <linux/dma-mapping.h>
int main() {
printf("Hello World\n");
return 0;
I'm starting to think that I'm making it more difficult than it should be.
Could anyone give me some advise how to successfully compile that small snippet? I would really appreciate it.
Regards,
Leroy

Hello Leroy,
Hmmm okay I found the one that I was thinking of:
http://forums.xilinx.com/t5/Embedded-Linux/AXI-DMA-with-Zynq-Running-Linux/m-p/523105#M10658
There's a presentation there with some code. About halfway down the pdf is an explanation of the software architecture for the AXI DMA linux driver and an explanation of where you need to add your application-specific layers and an example of doing so.
As far as compiling, you really need two pieces still (bear in mind, I'm a little out of my area of expertise talking about the linux software side, so someone with more knowledge may correct the finer details. This is based on what I've gathered...):
1) Kernel module to interface from the driver to userspace (for simplicity, you might use UIO for this like the second pdf that linnj posted in that link)
2) Some application that runs in userspace that communicates with 1 above.
For 1, you don't use SDK. You build a cross compile environment dependent on your kernel configuration and follow build steps:
http://www.tldp.org/LDP/lkmpg/2.6/html/x181.html
For 2, you'd use SDK as you are to build a Linux 'Application' (the word seems to have the connotation of running in userspace).

Number of DMA Channel on System

I need to log 16 (my be 32 later) simultaneous channel at the same time.
Is the limit of DMA chanels a windows system problem or just a card problem?
I understand that there is a limited number depending on the operating system.
So I cannot use 4 6601E cards (4 chanels each)at the same time on a PC.
I am told my NI that I could us PXI rack with a number of 6115 cards and an embeded controller running Window but I can not see that this would resolve the DMA problem unless it was a modified window system.
The other problem I see is that if Window 2000 or XP configers the cards to use he same chanel, Window will not let you change anything youself as all seeting are allway grayed out.
Judging my the large number of post on DMA perha
ps NI should write a white paper detaiing all the problems.
Thanks in advance fr your help.
Colin

Hello Colin,
Back with the ISA boards the limit of DMA channels was due to the computer itself. Now with PCI, DMA is handled by the PCI board itself. There has to be separate DMA controller hardware for each DMA channel. Our controller chip suppports up to 3 DMA channels. So I wouldn't say that this is a problem really. It's simply what the card offers, similar to the number of counters that is on the board.
There are fewer DMA channels than counters because 1) more DMA controllers would be more expensive, 2) Most applications probably would not require DMA channels for every counter. Interrupts may be sufficient for slower acquisitions or the the counters may be used for pulse generation which also wouldn't require DMA.
I guess I don't know enough abo
ut your application to comment on the 6115 suggestion. The 6115 is an analog simultaneous sampling board, but they only have 2 counters each. Perhaps it was suggested that you acquire this data with analog sampling. The advantage to this is that you can use the same DMA channel for all analog channels being scanned which would probably be a good alternative for your application.
Russell
Applications Engineer
National Instruments
http://www.ni.com/support

How many DMA Channels does my device have?

I would like to know how I can find out (progammatically) how many DMA channels my device has. I am using the DAQmx driver. Other than with the traditional DAQ I can't find out anything about my device but the "type" and the "serial number". Where can I get some more details about the device (not in the MAX - I want to know it in my program) with DAQmx?
My intention is to find out how many DMA Channels the device has and depending on how many Channels I need - I am using "interrupts" instead of DMA.
Somewhere in the KB of Ni was written that the NI-DAQ 6.9.... realizes automatically how many DMA Channels are available and how many I would need - and so he takes "interrupts" for the rest.
It seems that they did a "step bac
kwards" because with the NI-DAQ 7.2 it doesn't work automatically if I need DAQmx VI's.
Does somebody know anything that would help me to solve this problem?
Thanks.

Sorry! I posted my first revision of the answer.
Here is what I meant to say:
Hello,
According to this KnowledgeBase, DAQmx and Traditional DAQ behave the same. Are you seeing something different?
As far as a workaround goes, all you have to do is trap the No DMA error. This error should be -200251. So in software, if you receive error -200251, then you need to configure the board to use interrupts, and then start the task again.
How to configure the board for interrupts differs from the four different DAQmx API�s (C, C++, DotNET, and LabVIEW). If you are unclear about how to do this in your environment, please let us know, and we can find
out.
Best regards,
Justin T.
National Instruments

Number of DMA channels

如題，
我手邊有9636/9633兩張卡，
手冊上都是寫Number of DMA channels=5
請問這個數量跟FIFO Target to host DMA是一樣的意思嗎?
因為我設超過3個FIFO Target to host DMA，就會出現錯誤。
還有FPGA的FIFO最大個數是多少?
因為設3個FIFO Target to host DMA+2個FIFO Target scoped
有時候可以過，有時不行，有時程式還會閃退，真是OOXX
附件:
2013-05-30_151309.jpg ‏45 KB

http://www.ni.com/pdf/manuals/372596b.pdf
Number of DMA channels
http://digital.ni.com/public.nsf/allkb/22E2CE79F77B27508625794C00188265
http://digital.ni.com/public.nsf/allkb/470FF5EE8FD677F58625760A007562B9
您的應用為何?

Using ni-daq 7.1 traditional for AT-AI-16XE-10 first DMA channel doesn't respond

when using ni-daq 6.9.3 with AT-AI-16XE-10 it works OK!.using ni-daq 7.1 traditional first DMA channel does not respond.help please!

"polyplay26" wrote in message
news:50650000000800000056C30000-1077587809000@exchange.ni.com...
> when using ni-daq 6.9.3 with AT-AI-16XE-10 it works OK!.using ni-daq
> 7.1 traditional first DMA channel does not respond.help please!
What OS? Do you have a sound card?
Mohan Pawar

AXI DMA velocity and DCache doubts

This is a 2 question in one thread.
I'm basing my model on the matrix multiplication example,
First set of questions:
After some optimizations I have now a MM2S velocity of 1009 Mbytes/s and a S2MM velocity of 383 Mbytes/s.
1.1- Why is S2MM so slow when comparing to MM2S?
1.2- Are these the maximum velocities that you think I can get? Currently I'm not using interrupts and just waiting for each transfer to end before continuing. If I use interrupts will it be faster?
Second set of questions:
Following some advices I am going to divide my 512x512 matrices in 32x32 ones and treat each of them separately, since the Zedboard resources are not that big.
I already tested my design and the first 32x32 matrix is properly normalized. Input and output values are correct. However if I try and do a for cycle for all the matrices, the results are not correct and I think this is related to the cache flush and invalidate.
Here's my code:
#define DIM 32
//Start my IP block and enable auto-restart (doubts about this..)
XMm2s_Start(&BRAM_func);
XMm2s_EnableAutoRestart(&BRAM_func);
for(i=0;i<LIMIT;i++){
mm2s_bufferPtr=(u32 *)(SLOPE_ADDR+i*DIM*DIM*4);
result_Ptr =(u32 *)(FINAL_ADDR+i*DIM*DIM*4);
Xil_DCacheFlushRange((u32)mm2s_bufferPtr,DIM*DIM*4);
Xil_DCacheFlushRange((u32)result_Ptr,DIM*DIM*4);
Status = XAxiDma_SimpleTransfer(&axi_dma, (u32)mm2s_bufferPtr, DIM*DIM*4, XAXIDMA_DMA_TO_DEVICE);
if (Status != XST_SUCCESS)
xil_printf("ERROR! Failed to kick off MM2S transfer!\n\r");
return XST_FAILURE;
while (XAxiDma_Busy(&axi_dma,XAXIDMA_DMA_TO_DEVICE));
// Kick off DMA S2MM transfer
Status = XAxiDma_SimpleTransfer(&axi_dma, (u32)result_Ptr, DIM*DIM*4, XAXIDMA_DEVICE_TO_DMA);
if (Status != XST_SUCCESS)
xil_printf("ERROR! DMA transfer from Vivado HLS block failed!\n\r");
return XST_FAILURE;
while (XAxiDma_Busy(&axi_dma,XAXIDMA_DEVICE_TO_DMA));
print_matrix(result_Ptr,DIM,DIM);
Xil_DCacheFlushRange((u32)result_Ptr,DIM*DIM*4);
I already read this carefully about DCacheFlush and DCacheInvalidate but I still clearly have not understood very well.
Note: In the linker script I changed the heap and stack sizes to 10Kbytes instead of 1Kbyte.
Ty very much in advance for the help.

Hello jmales,
Right now my main IP (designed with Vivado HLS) is receiving a 32x32 matrix of floats. So, everytime I call my IP block within SDK I transfer 4096 bytes with the MM2S and then 4096 back with the S2MM transfer. So is 4096 my bandwidth ?
Oh okay, I see what you mean. The remaining question to answer first is:
- How often do you need to transfer a new 32x32 matrix? Or probably more useful question is how often do you need to transfer the 512x512 matrices? In other words, how fast are you acquiring new 512x512 matrices. What is your sample rate. This will tell you how much bandwidth you need.
If you only take in a new matrix every 10 seconds, then we only need to move data at a rate of 512 * 512 * 4 (bytes) / 10 = ~105KB/s in which case we don't really care about DMA efficiency because data is coming in so slowly. All we need to do is clock the DMA in the MHz range and you'll easily be able to keep up. The DMA will be sitting idle while we wait for new matrix for a while anyway, so any overhead associated with setting up the next transfer will be completely eclipsed and inconsequential. However, if you're taking in a new matrix every 10 milliseconds, we need to move data at 512*512*4/10e-3 = ~105MB/s which becomes a more difficult problem to solve and DMA efficiency may become a larger factor.
Another thing to think about is latency. Do you care about the absolute time (in milliseoncs) from when you acquire your matrix until it arrives at it's final destination? This will affect the rate that you clock your accelerator hardware (including DMAs, interconnects, etc). Take our 10 second matrix acquisition rate example. Even though the data rate is slow, if we need to pass data from DDR to accelerator, perform the matrix multiplication, then send data back to DDR all under 10 milliseconds, then you'll need to run your DMA operations faster. For minimal latency, every clock cycle counts so DMA configuration overhead might not be acceptable.
I was looking into this and actually posted a new thread regarding that meanwhile. So if I set the frequency of the MM2S and S2MM ports to 200MHz and the frequency of my custom IP block to 100Mhz, a FIFO ow 2 FIFOS will make sure everything runs smoothly?
Reading the other thread, I want to be clear about which problem this will solve. Doing this will ensure that your 100MHz clock domain will receive a continuous stream of data (i.e. no bubble cycles where the accelerator is not taking in new data). This is because the FIFO will have data in it which the accelerator can be processing while the DMA is being configured for the next transfer.
From a raw bandwidth (MB/s) perspective, this won't be as high as just running everything at 200MHz and allowing for those handful of buble cycles where the DMA is being reconfigured.
Maybe running some number will help to show the distinction:
1) FIFO case where you run processing at 150MHz with no buble cycles (in the processing clock domain) due to DMA downtime. 150MHz * 4 bytes per clock * 100% efficiency = 600MB/s
2) No FIFO, everything runs at 200MHz, DMA transfer length is 32*32 = 1024 cycles (or 4096 bytes), and say it takes 20 cycles to reconfigure the DMA for each transfer. The efficiency is 1024/(1024+20) = ~98%. So total bandwidth is 200MHz * 4 bytes per clock * 98% = 784MB/s
2) Again, no FIFO and everything runs at 200MHz with 20 cycles to reconfigure the DMA, but this time lets say we transfer the data one row at a time so our transfer length is 32 cycles (or 128 bytes). Now our efficiency is only 32/(32+20) = ~61.5%. So total bandwidth is 200MHz * 4 bytes per clock * 61.5% = 492MB/s
So if we figure out the number of matrices you need to process per second and the input-to-output latency requirements, then we can start deciding on architectural stuff about how best to move the data around.

How do I AI config for SCXI multiple non-contiguous channels

I need to configure a measurement of with multiple groups of thermocouple channels.
Using LV 5.1.1 (could use 6, but I am supporting lots of code built with 5.1.1), DAQ 6.8.1 (can up to 6.9.1 if it matters), PXI-6052E, SCXI-1102, SCXI-1303 (or TC-2095).(using SCXI addressing).
The problem occurs when I try to configure multiple scan lists with gaps between channels.
(see LV DAQ SCXI example SCXI-1102/1127/1101 Thermocouple)
example channel list:
ob1 ! sc1 ! md1 ! cjtemp
ob1 ! sc1 ! md1 ! 0:3
ob1 ! sc1 ! md1 ! 5:9
This gives an error: -10370 in AI Group Config.
Likewise if I use an individual channel in each address string. like:
...md1 ! 0
...md1 ! 1
...md1 ! 3
But, I can skip channels betwe
en cjtemp and the first channel of the next scanlist without error.
Also, I can add scan lists for other modules, like:
...md1 ! 0:3
...md1 ! 4:8
...md3 ! 12:14
without error!
What I really want to do is to do AI Config first for all channels, then start, then loop on AI Read and some processing & storage.
When I loop through the channel address lists (strings with contiguous channel sets e.g. 3:6) I get the same task # for all config calls. Then when I loop through the AI Start's for each , I get an error -10609 in AI Clock Config.
The thing is that I cannot necessarily have all contiguous channels, and I don't want to go through a sequence of {AIConfig, AIStart, AIRead, AI CLear} for each scanlist each time through. That takes too much time and resources.
Eventually I want to configure multiple non-contiguous scanlists in multiple SCXI modules.
But, for right now I need to do this for one SCXI module.
Anyone have any ideas?
How can I approach this.
Thanks
Dave

Dave
Check the following link into the NI Knowledgebase (if you haven't already)
which I think explains your situation.
http://digital.ni.com/public.nsf/3efedde4322fef19862567740067f3cc/02a55e1f39
e8bd15862567e700577877?OpenDocument
Bottom line is you will not be able to skip channels on any SCXI module
other than the SCXI-1112. You will need to include the channels in your scan
list then discard the data later.
Either that or as the Knowledgebase suggests, use Virtual Channels. You can
then miss channels out in the scan list as you require. They actually get
scanned but NI-DAQ discards the data for you.
Ian Bell
NI UK
"Dave Karon" wrote in message
news:[email protected]...
> I need to configure a measurement of with multiple groups of
> thermocouple channels.
> Using LV 5.1.1 (could use 6, but I am supporting lots of code built
> with 5.1.1), DAQ 6.8.1 (can up to 6.9.1 if it matters), PXI-6052E,
> SCXI-1102, SCXI-1303 (or TC-2095).(using SCXI addressing).
>
> The problem occurs when I try to configure multiple scan lists with
> gaps between channels.
> (see LV DAQ SCXI example SCXI-1102/1127/1101 Thermocouple)
> example channel list:
> ob1 ! sc1 ! md1 ! cjtemp
> ob1 ! sc1 ! md1 ! 0:3
> ob1 ! sc1 ! md1 ! 5:9
> This gives an error: -10370 in AI Group Config.
> Likewise if I use an individual channel in each address string. like:
> ..md1 ! 0
> ..md1 ! 1
> ..md1 ! 3
>
> But, I can skip channels between cjtemp and the first channel of the
> next scanlist without error.
> Also, I can add scan lists for other modules, like:
> ..md1 ! 0:3
> ..md1 ! 4:8
> ..md3 ! 12:14
> without error!
>
> What I really want to do is to do AI Config first for all channels,
> then start, then loop on AI Read and some processing & storage.
> When I loop through the channel address lists (strings with contiguous
> channel sets e.g. 3:6) I get the same task # for all config calls.
> Then when I loop through the AI Start's for each , I get an error
> -10609 in AI Clock Config.
>
> The thing is that I cannot necessarily have all contiguous channels,
> and I don't want to go through a sequence of {AIConfig, AIStart,
> AIRead, AI CLear} for each scanlist each time through. That takes too
> much time and resources.
>
> Eventually I want to configure multiple non-contiguous scanlists in
> multiple SCXI modules.
> But, for right now I need to do this for one SCXI module.
>
> Anyone have any ideas?
> How can I approach this.
> Thanks
> Dave

Multiple Endpoints Single Channel

I am working on a project, that requires instancing of our
flex application. One idea that I came up with was to allow for
multiple urls to access the same data based on several variables.
One key components for this idea to work is being able to use
multiple endpoints with in the same channel in my
services-config.xml file.
Right now this is what my channel setup looks like.
<channels>
<channel-definition id="cfamf"
class="mx.messaging.channels.AMFChannel">
<endpoint uri="
http://admin.mydomain.com/flex2gateway/"
class="flex.messaging.endpoints.AMFEndpoint"/>
<properties>
<polling-enabled>false</polling-enabled>
<serialization>
<instantiate-types>false</instantiate-types>
</serialization>
</properties>
</channel-definition>
<channel-definition id="cfamf"
class="mx.messaging.channels.AMFChannel">
<endpoint uri="
http://user.mydomain.com/flex2gateway/"
class="flex.messaging.endpoints.AMFEndpoint"/>
<properties>
<polling-enabled>false</polling-enabled>
<serialization>
<instantiate-types>false</instantiate-types>
</serialization>
</properties>
</channel-definition>
</channels>
Ideally I would prefer it to act like this.
<channel-definition id="cfamf"
class="mx.messaging.channels.AMFChannel">
<endpoint uri="
http://admin.mydomain.com/flex2gateway/"
class="flex.messaging.endpoints.AMFEndpoint"/>
<endpoint uri="
http://user.mydomain.com/flex2gateway/"
class="flex.messaging.endpoints.AMFEndpoint"/>
<properties>
<polling-enabled>false</polling-enabled>
<serialization>
<instantiate-types>false</instantiate-types>
</serialization>
</properties>
</channel-definition>
</channels>

one AP will only serve a single channel per spectrum. If you have multiple SSID they can be on the same channel with no issue, so long as you're not running more than 4-5. After that you start to cause issues inside your own network.
If you absolutely had to run them on different channels, you would need multiple AP to accomplish that.
But as I said, you shouldn't need to.
Steve
Sent from Cisco Technical Support iPhone App

Multiple AXI DMA channels on zedboard

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