Generate Accelerating Quadrature Pulses

Hi,
I need to generate pulses that simulate a quadrature encoder with acceleration. I have digital output and counter output NI devices available. I have done vi's that start with the quadrature pattern as a 1-D array of Integers and clock those out to a digital port. This is fine for fixed speed output. It allows me to output a fixed number of pulses at a fixed speed, but it doesn't easily allow acceleration.
I need to be able to do accelerating pulse trains. This would simulate, for instance, a real encoder attached to a motor that is accelerated from one speed to another. It would be most ideal if I could accelerate from a fixed speed to another fixed speed using a fixed number of pulses for the whole pattern. This would simulate a device that has distance, speed and acceleration control simultaneouly, and that is exactly the type of device I am simulating.
Max pulse frequency will be a bit under 130kHz.
The most ideal situation would be for the width of each pulse in the train to change proportionally as the frequency changes, i.e. a smooth frequency ramp.
Thank you.
Mark Holm

Mark,
This was a fun little challenge.
It steps through a range of periods from beginning period to ending period. Internally the quarter period is used to allow generation of the quadrature signal by dividing by the frequency by 4. All timing inside the loop is done with integers to simplify comparisons.
The acceleration increment, Tau, is used to determine when the period changes. The accelration rate, dT/dTau, determines the amount of change in period at each increment Tau.
When iteration counter i divided by the current period has a remainder of zero, the encoder value is updated. The encoder consists of two booleans on shift registers with logic to implement a two-bit grey-code counter.
The booleans are changed to integers and offset to display on both a chart and a graph. The small delay in the grey-code case structure sets the speed of the displays.
The loop will stop when the Ending period is reached or when the user presses Stop. With the default values it runs about 10-15 seconds on my computer.
The VI was developed in LV 2013 and saved back to LV 8.0.
Lynn
Attachments:
Accelerating encoder sim.vi ‏33 KB

Similar Messages

Generating frequency dependant square pulse and making it digital

trying to generate a square wave pulse at a specific frequency
it would be great if its simple as setting the amount of frequency (i.e., 50 , 50 pulses per sec)
but it gets complicated because of the sample rate
my problem is to convert it to digital and i don't know whats wrong
i attached a pic of my block diagram
as you can see, one pulse has frequency F, the other F/2, and lastly F/4
i need it to be compatible with the VI attached as well. can anyone help? thanks in advance!
Message Edited by sdkpark on 10-10-2009 12:19 AM
Attachments:
Create Digital Waveform.vi ‏20 KB
Correlated Dig Write With Counter.vi ‏31 KB

Hello again Sdkpark,
Apologies the message I was writing didn't include my full post. Take a look at this great community example for a prebuilt solution to what I believe you're trying to accomplish:
http://decibel.ni.com/content/docs/DOC-5763
Let me know if this isn't what you're looking for and I'll reply back. Have a great day!
-John Sullivan
Analog Engineer

How to generate a delayed retriggerable pulse using only one counter with PXI 6070E card

Hi
I have a problem in generating a retriggerable delayed pulse with a single counter(triggered through a signal at gate) using PXI 6070E card. VI was developed in NI LabVIEW traditional DAQ Ver.7.1. I have used the "delayed pulse generator config" VI and a "Start counter" & "Stop counter" VIs for the purpose. But there is no output seen at the out terminal of counter. So I introduced a "wait" VI and set it to 1 sec. Now the pulse output appears but some pulses are missing mometarily after every 1 sec interval. (any solution for this)
I have gone through a few similar requests in the forum but they suggest either to use two counters or to generate a finite pulse train which does'nt fit my application. Moreover PXI 6070E has only 2 counter timers. I am already using one counter to measure the frequency of a pulse train(signal 1). The application requires to generate a delayed retriggerable pulse for every pulse in signal 1. So I have only one counter left.
Can I measure the frequency of signal 1 by analog means.? so that I can use two counters for pulse generation. (Signal 1 is a TTL signal).
Request some help.
Thanks in Advance
Regards

A finite pulse train (N_Pulses >= 2) does require the use of 2 counters on most of our older hardware including your 6070E. If you're just talking about generating a single retriggerable pulse, you would only need one counter.
Here's an example in Traditional DAQ that shows you how to set a retriggerable pulse generation (it also allows you to adjust the characteristics of the pulse on-the-fly).
If you're writing a new program, you might consider switching to DAQmx as it supports NI's latest hardware and recent OSes should you ever need to upgrade. Traditional NI DAQ is no longer in active development. Here's an example of how to implement a retriggerable pulse generation in DAQmx. You should take note that you can't use the two drivers to simultaneously talk to the same piece of hardware, although you should be able to go back and forth by resetting the Traditional DAQ driver before switching to DAQmx.
Best Regards,
John Passiak

On E series Card with 2 counters I want to generate a fixed length pulse train and want to continuously monitor it.

On E series Card with 2 counters I want to generate a fixed length pulse train and want to continuously monitor it.

Depending on the software you are using, there are many shipping examples and example programs on the web that illustrate generating a finite pulse train. The E series boards have the DAQ-STC counter/timer chip, and so make sure you search for DAQ-STC examples. I have included links to a LabVIEW example and Measurment Studio Example in Visual Basic.
Generate finite pulse train in LabVIEW.
http://eagle.ni.com/stage/we/niepd_web_display.DISPLAY_EPD4?p_guid=B45EACE3DA2156A4E034080020E74861&p_node=DZ52328&p_submitted=N&p_rank=&p_answer=&p_source=Internal
Generate finite pulse train in Visual Basic with Measurement Studio
http://eagle.ni.com/stage/we/niepd_web_display.DISPLAY_EPD4?p_guid=B45EACE3D96156A4E034080020E74861&p_node=DZ52328&p_submitted=N&p_rank=&p_answe
r=&p_source=Internal

Buffered event counting. Why can't I explicitly sequence generating the Sample Clock Pulse and reading the counters?

At irregular occasions I need to grab counts from several counters, and buffering the counts must be done simultaneously for all counters. I'm modeling my approach after zone.ni.com/devzone/cda/tut/p/id/5404 which someone kindly pointed out in an earlier thread. However, that example only uses one counter, and you can't test the synchronization with only one counter, so I am using two counters configured the same way, and they're wired to a single benchtop signal generator (for example at 300 kHz).
What I want to do, I can test in a loop with a somewhat random wait in it. I want to drive a hardware digital output line high for a few ms and then low again. The hardware line is physically connected to terminals for my timing vi's Sample Clock Source and so will cause them to buffer their counts for later reading. After I pulse this line, when I know new good buffered counts await me, I want to read both my counters. If their bufferings are simultaneous, then each counter will have counted the same number of additional counts since the last loop iteration, which I can check by subtracting the last value sitting in a shift register and then subtracting the two "additional counts" values and displaying this difference as "Diff". It should always be 0, or occasionally +1 followed immediately by -1, or else the reverse, because buffering and a count could happen practically at the same moment.
When I do this using a flat sequence to control the relative timing of these steps, so the read happens after the pulse, the counters often time out and everything dies. The lengths of time before, during, and after the pulse, and the timeout value for the read vi, and the size of the buffer and various other things, don't seem to change this, even if I make things so long I could do the counting myself holding a clipboard as my buffer. I've attached AfterPulse.vi to illustrate this. If I get 3 or 10 or so iterations before it dies, I observe Diff = 0; at least that much is good.
When I use two flat sequences running in parallel inside my test loop, one to control the pulse timing, and the other to read the counters and do things with their results, it seems to work. In fact, Diff is always 0 or very occasionally the +/- 1 sequence. But in this case there is nothing controlling the relative timing such that the counters only get read after the pulse fires, though the results seem to show that this is true. I think the reads should be indeterminate with respect to the pulses, which would be unreliable. I don't know why it's working and can't expect it to work in other environments, can I? Moreover, if I set some of the pulse timing numbers to 1 or 2 or 5 ms, timeouts start happening again, too. So I think I have a workaround that I don't understand, shouldn't work, and shouldn't be trusted. See SeparateSequence.vi for this one.
I also tried other versions of the well-defined, single sequence vi, moving the counter reads to different sequence frames so that they occur with the Sample Clock Source's rising edge, or while it is high, or with the falling edge, and they also often time out. I'll post these if anyone likes but can't post now due to the attachment limit.
Here's an odd, unexpected observation: I have to sequence the reads of the counters to occur before I use the results I read, or else many of the cycles of this combine a new count from one counter with the one-back count from the other counter, and Diff takes on values like the number of counts in a loop. I though the dataflow principle would dictate that current values would get used, but apparently not so. Sequencing the calculations to happen after the reads fixes this. Any idea why?
So, why am I not succeeding in taking proper control of the sequence of these events?
Thanks!!!
Attachments:
AfterPulse.vi ‏51 KB
InSeparateSequence.vi ‏49 KB

Kevin, thanks for all the work.
>Have you run with the little execution highlighting lightbulb on? -Yes. In versions of this where there is no enforced timing between the counter and the digital line, and there's a delay inserted before the digital line, it works. There are nearly simultaneous starts on two tracks. Execution proceeds directly along the task wire to the counter. Meanwhile, the execution along the task wire to the digital high gets delayed. Then, when the digital high fires, the counter completes its task, and execution proceeds downstream from the counter. Note, I do have to set the timeout on the counter longer, because the vi runs so slowly when it's painting its progress along the wires. If there is any timing relationship enforced between the counter and the digital transition, it doesn't work. It appears to me that to read a counter, you have to ask it for a result, then drive the line high, and then receive the result, and execution inside the counter has to be ongoing during the rising line edge.
>from what I remember, there isn't much to it. There really aren't many candidate places for trouble. A pulse is generated with DIO, then a single sample is read from each counter. -Yup, you got it. This should be trivial.
>A timeout means either that the pulse isn't generated or that the counter tasks don't receive it. - Or it could mean that the counter task must be in the middle of executing when the rising edge of the pulse arrives. Certainly the highlighted execution indicates that. Making a broken vi run by cutting the error wires that sequence the counter read relative to the pulse also seems to support that.
>Have you verified that the digital pulse happens using a scope? -Verified in some versions by running another loop watching a digital input, and lighting an indicator, or recording how many times the line goes high, etc. Also, in your vi, with highlighting, if I delete the error wire from the last digital output to the first counter to allow parallel execution, I see the counter execution start before the rising edge, and complete when the line high vi executes. Also, if I use separate loops to drive the line high and to read the counter, it works (see TwoLoops.vi or see the screenshot of the block diagram attached below so you don't need a LV box). I could go sign out a scope, but think it's obvious the line is pulsing given that all these things work.
>Wait! I think that's it! If I recall correctly, you're generating the digital pulse on port0/line0... On a 6259, the lines of port 0 are only for correlated DIO and do not map to PFI. -But I'm not using internal connections, I actually physically wired P0L1 (pin 66) to PFI0 (pin 73). It was port0/line1, by the way. And when running some of these vi's, I also physically jumper this connection to port0/line2 as an analog input to watch it. And, again, the pulse does cause the counter to operate, so it clearly connects - it just doesn't operate the way I think it is described operating.
For what it's worth, there's another mystery. Some of the docs seem to say that the pulse has to be applied to the counter gate terminal, rather than to the line associated with the sample clock source on the timing vi. I have tried combinations of counter gate and or sample clock source and concluded it seems like the sample clock source is the terminal that matters, and it's what I'm using lately, but for example the document I cited, "Buffered Event Counting", from last September, says "It uses both the source and gate of a counter for its operation. The active edges on the gate of a counter is used to latch the current count register value in a hardware register which is then transferred via Direct Memory Access...". I may go a round of trying those combinations with the latest vi's we've discussed.
Attachments:
NestedSequences.png ‏26 KB

HOW TO GENERATE FINITE AND CONTINUOUS PULSE TRAIN WITH USB6216 AT THE SAME TIME?

Hello.
I am using a USB6216 DAQ and need to generate a 20 kHz signal using the
ct0 output and at the same time I need to generate a finite number of
pulses, say 9, on a software trigger using the second counter output
ct1.
Currently, I have two VIs that can do this separately, but when I want
to integrate these into one single VI y get an error in the finite
pulse train for ct1 that indicates that the requested task is already
reserved. I am thinking this has to do with the fact that maybe both
types of task use the same timebase but I have not found the way to
solve this problem.
Any help would be very much appreciated.
Thank you.
Sincerely
JSL

Hello.
If anybody is interested, the problem is solved.
There is no resource confilct if I generate the 20 kHz continuous pulse
signal using the frequency out terminal, and this way I can use both of
my counters as I please with no problems.
It's kind of fun to answer one's own questions...
Sincerely
JSL

Generate a delayed counter pulse

I am posting this to see if anyone can shed any light on various DAQmx operations with counters. I appear to have found a solution for the project but various counter operations are certainly not well documented and the notes I am posting may help anyone trying to do something similar.
The project is to monitor an analog input channel and when a certain criterion is met generate a pulse with a specified width at a specified delay from the event. It is being done in a LV Real Time system. Initially I tried to start a counter task within a loop, wait until done and stop the task. What I have found is that it takes a long time (of the order of 10-100's of ms) for the start task to return and the wait until done doesn't reliably return at the time the counter pulse is finished being generated. Other people seem to have found the same problem. This is described in the part 1 attachment and the attached vi.
The other way to do it is with a retriggerable counter task and using a digital line on the same card to trigger the counter. Then the way the counter works if there is a single pulse or multiple pulses is different. The way low time and high time are interpreted is odd. This is described in the part 2 attachment with screenshots from Scope captures. I have a proposed solution but I'm not sure if it is the best way to do it.
Any suggestions appreciated.
Attachments:
Generate delayed Counter Pulse problem part 2.doc ‏108 KB
Generate delayed Counter Pulse Problem part 1.doc ‏25 KB
Generate Counter Pulse.vi ‏153 KB

Andrew,
If you want to start a counter output task based on an analog input you should use an analog trigger (if your device supports analog triggering). Take a look at the example Cont Acq Sample-Timed Loop-Analog Start.vi (in the example finder - search for "trigger") for how to set up an analog trigger in DAQmx. Also, you can use the Start.Delay property in the DAQmx Trigger property node to specify an amount of time to wait after the Start Trigger is received before generating the first sample
Michael P
National Instruments

Generate/Read Digital Pulse - What clock to use?

Hi,
I am using the NI cDAQ-9172 (with output module NI 9472 and input module (9421). I am trying to generate a pulse, run it through a system (just a resistor at this point) and then read it back into labview. I am able to generate the pulse with no problem, but anytime I try to read it I get an error regarding the clock. Any suggestions?
Thanks,
Solved!
Go to Solution.
Attachments:
Generate and Read Pulse.vi ‏30 KB

Looks like i figured it out. I had the clock said as hardware timed, but my hardware was wired wrong. After I corrected the wiring it worked, so that must have been the problem.

Generate 1 microsec TTL pulse

hi,
i wanted a particular DIO pin say DIO1 to be in high state for i micro sec.how should i implement this?i am using Labview 6i on win98,PCI-6024

sithara,
I assume that you want to generate a pulse that lasts for only 1 micro second in the high state. This would not be possible with a digital line, but it is easy to do with a counter. You can have single pulse generation to specify the delay and the length of the pulse. As soon as you use the internal 20 MHz time base the counter should work just fine. The DIO lines on that board are not really meat for high speed switching, but the counter will do. I'm sure you can fine some premade code for this.
Regards,
Gazoo!

Generating a delayed digital pulse

Hi,
I have two digital inputs, read via a DAQmx assistant, one represents a one pulse per revolution, the other
one pulse per crank angle degree (hence 360 per rev) which are generated by an optical encoder
attached to the shaft of a small engine setup.
What I would like to do is to output a single pulse 'n' crank angle (where n could be changed) pulses after
the revolution pulse. The output would be via another DAQmx assistant (ideally, as this is what I have been working
with so far). However I can only find something that will delay my signal on a time basis, rathert than sample
basis,
Any help appreciated.
Sandra

There is a point by point vi that will delay based on cycles of new data entering the vi. It holds the data value until the number of cycles is up. This might be a place to start. You can go inside this Zero-Order Hold PtByPt.vi to see how it works. This is in 7.0 format.
Attachments:
zero hold pt by pt.vi ‏38 KB

How to generate an (re-) synchronized pulse train

Hello,
using a PCI-6601
I want to generate an endless pulse train of (e.g. 80Hz, high==low) synchronized to an external clock (ca.1Hz, ca 5ms pulse width).
The output should _re_synchronize with the clock if there is a clock signal but if one clock-pulse is missing it should continue hoping for the next.
It should look like this:
Perfect:
A1) tt________________tt________________tt_________...
A2) ooo___ooo___ooo___ooo___ooo___ooo___ooo___ooo__...
    0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5_...
Output is too fast:
B1) tt_________________TT________________tt________...
B2) ooo___ooo___ooo___oxxx___xxx___xxx___xxx___xxx_...
    0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5_...
Output is too slow:
C1) tt_______________PP________________tt__________...
C2) ooo___ooo___ooo__xxx___xxx___xxx___xxx___xxx___...
    0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5_...
Clock is missing:
D1) tt________________._________________tt__________...
D2) ooo___ooo___ooo___xxx___xxx___xxx___xxx____xxx__...
    0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__...
The external clock is assumed to be "the truth", so the pulse width for the 80Hz output is recomputed from time to time
by measuring the clock and then setting then output pulse width.
Until now I used register programming but this is not a must.
The examples I've found either generate finite pulse trains or the sync only once.
Is there a way to do what I want without software interaction?
Thanks in advance
Toni Schilling

I have a possible idea for you, but my experience is with LabVIEW so I can't offer any help with register programming, interrupt callbacks, etc. Also, the continuous syncing will have to be a software function that continuously performs cycles of measure/adjust, measure/adjust, measure/adjust...   I know of no way to set up the hardware to do this autonomously.
The approach I would take is to add another counter task and a little extra wiring. The other task will be for "Two Edge Separation", and you want to measure from the active (lead) edge of the master clock to the passive (trail) edge of your sync'ed pulse train. There's a reason NOT to measure to the active (lead) edge of your pulse train and it's because counters can only measure finite times of at least 2 timebase cycles. Whereas you would *like* to have an actual two-edge separation time of 0 between the lead edges. That just seems like the kind of detail that's gonna burn you sooner or later.
Let's just suppose the master clock is nominally about 1 Hz and your pulse train is nominally 100 Hz and 50% duty cycle so I can talk through details with some specifics. Whenever the two lead edges are truly sync'ed, you'll measure a 0.005 sec two edge separation time from the master clock to your pulse train's trail edge. If you measure slightly *less* than that, your pulse train is going just a little too fast and needs its freq slightly reduced. If you measure slightly more, then your pulse train is too slow and needs its freq slightly increased.
It is probably quite likely that you *cannot* expect to maintain perfect sync *without* constant monitoring and adjustment. Fundamentally, you can only produce pulses with high and low times that are an integer multiple of the 6601's timebase of 20 MHz. That card's oscillator won't be perfect, nor will it be utterly constant over temperature variations, etc.   So its idea of a perfect 100 Hz pulse train will in fact be very very close but not *actually* perfect.
And your ability to adjust the frequency away from a nominal 100 Hz will only be possible in discrete steps.
A 100 Hz pulse train takes 200000 cycles of the 20 MHz clock. If you adjust your square wave to take 199998 or 200002 cycles, you can produce a nominal freq of 100.001 or 99.999 Hz. Those are the smallest increments away from 100.00000000 that are possible with a 50% duty cycle.
Statistically, it's very unlikely that the frequency needed to perfectly match the external master clock is even *possible* to produce exactly. I think you need to *expect* an imperfect sync with continual subtle adjustments to your pulse train. If you watched the signals on a scope while triggering from the master clock, I think you should expect to see your pulse train oscillating back and forth by some small amount, perhaps in the microsecond realm.
Summary (for 1 Hz master clock, 100 Hz user pulse train at 50% duty cycle):
Measure two-edge separation from lead edge of master clock to trail edge of user pulse train. Use units of "Ticks" with 20 MHz timebase. Nominal expected value when sync'ed is (1/2)*(20 MHz / current user freq) = 100000.
Subtract measured ticks from nominal to produce your "error signal".
Use current error signal its recent history in a control algorithm to determine the amount of adjustment to make to your pulse train. Hint: it will probably NOT be correct to directly change the user pulse width by an amount equal to the error signal. I suspect that you'll want to pay closest scrutiny to the derivative of the error signal. Note also that the correct AMOUNT of adjustment will depend on the RATE at which you run your measurement / adjust loop.
Change user pulse specs on-the-fly.
Return to step 1.
Caution: Let's suppose your software measurement / adjust loop runs at a nominal 10 Hz. From the time you make an adjustment until the next time you do a measurement, your user pulse train will have generated almost 10 cycles with the recently-adjusted specs. If you weren't careful to make your previous adjustment subtle enough, you'll find that you now have a *larger* error of the opposite sign, and you are well on your way to instability.
   You need to do an adjustment that lets you expect your *next* measurement to have an error close to 0.
-Kevin P.

How to generate a single output pulse on 64 different digital out lines (PCI-6513) each with a different start time relative to an event in a main program loop.

Long question.
I am running a main program loop of 60 msec. At one point in the loop I create a 64 element array of delay times. At that point I need to begin outputting a predefined single pulse to each of the 64 lines on my PCI-6513. Each line outputs the pulse with a starting delay set by the "delay time" in the array.
Each delay time is such that the pulses will be done before the next loop commands another one.
Thank You
Roger

Hi,
You have multiple ways of doing this, since there is no timing engine on the 6513 your code is going to control the output of the card, which is what we called “software timed”. If you take a look at the example called: “Write Dig Chan.vi”, you can individually control each line.
So to change the state of the line; since you have an array of delays time you can aid yourself with “stacked sequence structure” where in each frame you control the time it takes to go to the next frame and the data been written to the card.
Another option is using a state machine where each state write the data you want and you can also control the time between states. For further references take a look at this article Application Design Patterns: State Machines.
I hope it helps
Jaime Hoffiz
National Instruments
Product Expert
Digital Multimeters and LCR Meters

Generate a different width pulse using pxi-6542

Hello I want to use the board of PXI-6542 to generate a waveform, and the waveform has different width, but the width is a integer which is less than ten is multiplied by 0.1ms,and the multiply is random. The waveform is output through PXI-6542.Thank you for your help. bless vivian

Duplicate Post.

How to measure the frequency of a pulse being generated by a counter

Hi,
I am using labview 8.6 to generate 5 evenly spaced pulses for every 1 revolution of my shaft. However, I would also want to know the frequency of these pulses so I can determine the shaft speed. Since I am already generating the pulses using one of my counters, can I still tap into that or task another counter to measure the pulse frequency? If so, how? I have attached my code for generating the pulses and I am using an Ni 9401 module and an NI 9172 chassis. If someone can helo me modify the code to measure and tell me the pulse frequency as well, that would be really appreciated
Attachments:
autotrain2.vi ‏19 KB

You'd probably get a more coherent answer if you didn't bounce around from thread to thread so much...
How can I generate a pulse train from shaft encoder? (5/13)
pulse train from encoder (5/15)
how to measure rpm (5/20)
How to measure rpm using shaft encoder and labview (5/23)
This thread (also 5/23)
I see you ignored my suggestion from the other thread--Kevin's solution is good too but using an encoder task offers more noise immunity (I think this is probably the cause of the problem you reported on the other thread). You can fix it with digital filtering if you want to keep using a counter output instead of an encoder task. Noise during transitions is pretty common for a quadrature encoder.
A finite counter output task uses 2 counters on the 9172 (although you said 9174 earlier at one point--this wouldn't be the case on a 9174) so you wouldn't have one left to make your frequency measurement. With the solution you have now, you can change to continuous to free up a counter if you don't care about outputing an exact number of rotation's worth of pulses (I'm not sure if you do or not--I didn't read through all of the various threads relating to this application to find out).
For your actual question in this thread... Have you tried running one of the frequency measurement examples? From the code here I can't tell what you have tried (it just looks like a mangled version of the code Kevin gave to you in your other thread).
Best Regards,
John Passiak

Can I generate pulse trains on more than one counter output at the same time?

I have a PCI 6601 card with a BNC 2121 to connect the signals to two devices. The card is used as a trigger for both devices and I want to be able to generate pulse trains on two output channels at the same time, with a time delay between the two. How do I do that in Labview 7.1 Development with DAQmx?

I feel foolish for not being able to figure this out, but it still doesn't work. Attached is the VI I use now. Counter 0 generates a finite pulse train and I programmed Counter 1 to generate a retriggerable single pulse triggered by CtrOinternaloutput. I still get the same error message: -50103 The specified resource is reserved. The operation could not be completed as specified.
The same happens if I set the trigger for counter 1 at PFI36 (default output of counter 0) or any other PFI line. If I try a pulse train generation on only one of the counters, both work fine.
If I try the example in traditional DAQ for multiple counter outputs with phase delay, it works fine.
Can you tell me what I'm doing wrong?
Attachments:
Shutter_AND_lamp_trigger.vi ‏103 KB

Generate Accelerati​ng Quadrature Pulses

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Generate Accelerating Quadrature Pulses