Glitch on dc signal

Question

Hello,
I am using Analogue module PXI 6713 A[5] pin in PXI
chassis 1044, to generate a Glitch( amplitude 1.2V with a depth of 0.5V)  on a DC signal. The glitch on the DC signal
through A[5] pin is achieved in the following way.
Method 1: (Please refer Glitch_2ms.JPG and VMON_Ramp.vi
files)
1) Start generating the DC signal from 1.2V.
2) Once it reaches the 1.2V start decreasing the voltages
in steps of 0.1V until it reaches 0.5V.
3) Once it reaches 0.5V start increasing the voltages in
steps of 0.1V until it reaches 1.2V.
Repeat steps 1 , 2 and 3 ...
This way I am able to achieve the glitch width of 2ms
with a decrease of 0.1V /interval. But I would like to achieve the glitch of
width 1us or 10us. I followed below steps to generate the minimum glitch width.
Method 2: (Please refer Glitch_180us.JPG and
VMON_Ramp_debug.vi files)
1) Start generating 1.2V DC signal.
2) Immediately generate 0.5V DC signal.
Repeat steps 1 and 2.
But the glitch width I could able to achieve is only
180us which doesn’t meet my requirement of 1us.
The Labview source code for  both the 
methods  are attached.
Could you please give your inputs in order to achieve the
glitch width of 1us order.
Thanks.
Sincerely,
Srinath.
[email protected]
816 728 2134
281 274 2988.
Attachments:
2ms_180us.JPG ‏75 KB
VMON_Ramp.vi ‏30 KB
VMON_Ramp_debug.vi ‏26 KB

Answer 1

I believe I understand what you're trying to do. You cards maximum sample speed for single channel analog output is 1MS/s. This means that 1/1MS/s = 0.000001s/S is the minimum interval between samples that you can write. This is precisely 1 microsecond minimum dt. As a result, trying to write a glitch at 1microsecond means that it will be instantaneous and not ramped (there is no room to ramp because it would have to happen in the interval between 2 samples). Also, are you trying to make the clitch 2microseconds wide (1 down and 1 up)? That is reasonable as you can have 1 sample of down time at .5V and the rest up at 1.2V. Otherwise you're working on too small of a time scale (.5 microseconds down and .5 up is too small of an interval for the maximum sample speed of the card).
Also, if you're trying to do regenerative output (meaning you load a set number of samples to the card), you're going to have to make sure that the FIFO size (which is somewhere around 16k samples) is big enough to give you the appropriate interval upon which you want to re-trigger the glitch. In the case of that cards FIFO size this is a very small (16ms) interval. Is that a small enough interval for retriggering? You can also do it in non-regenerative mode which would allow you more control, however you'll need to be very careful about underflow issues. See the example in labview about continuous non-regenerative internal clock analog generation for an example of how to do this (should be in Hardware Input and Output->DAQmx->Analog Generation). If your "configurable time period" is smaller than around 16ms, you'll want to do things nonregeneratively. There may be a way to do it with some sort of complex triggering system, but I don't think the card is going to be capable of that, I think non-regenerative software methods are the only way to accomplish it on a larger time interval.
You may also (if this seems to daunting) wish to be put in touch with an alliance member who might be able to help you get the code written. It will cost a little, but if this will take a sizable chunk of your time it may be worth it.