Hall Pulse Simulator using 2 counters on 6025E card
Hello All,
I am trying to simulate DC motor hall pulses using 2 counters on the 6025E daq card. The phase shift between Hall1(ctr1) and Hall2 (ctr2) should be 90 Degrees. Based on the comments and suggestions on the forum, I have come up with a VI that could possibly do this.
I wanted to get some feed back on the attached VI and possible pointers if somethings need changes.
Your inputs will be highly appreciated. Its in LV 8.5
Thanks,
Praveen R
Attachments:
Hall Pulse Generator.zip 57 KB
Hi Praveen,
Your VI architecture is difficult to understand at first glance. It looks like you're trying to mimic an event-based program flow, so you may benefit from using an event structure rather than a while-case structure.
Also, you're using channels and tasks defined in MAX, so I can't see how this VI would (or wouldn't) get the behavior you're after. If you could document your code and explain in more detail your requirements and expectations, then I might be able to give some more insight. Also, outlining your algorithm would also help me understand if your code will do what you want.
Finally, National Instruments has a document about LabVIEW best practices that will help you program cleanly and efficiently.
Rules to Wire By
Joe Friedchicken
NI VirtualBench Application Software
Get with your fellow hardware users :: [ NI's VirtualBench User Group ]
Get with your fellow OS users :: [ NI's Linux User Group ] [ NI's OS X User Group ]
Get with your fellow developers :: [ NI's DAQmx Base User Group ] [ NI's DDK User Group ]
Senior Software Engineer :: Multifunction Instruments Applications Group
Software Engineer :: Measurements RLP Group (until Mar 2014)
Applications Engineer :: High Speed Product Group (until Sep 2008)
Similar Messages
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This simulation has several transmit and receive messages. The fastest message refresh rate is set to 50Hz (20 ms).
Hi,
Can you provide some more information about what hardware and software you are using? What is your application? Thanks!
JenK -
Generate delayed triggered pulse. Already have used both counters.
I need to generate sequence of 3 pulses. Each one is triggered with previuos one and has certain width. I have successfully used 2 counters on my 6713 card and I am wondering if there is any way to generate the third pulse. I thought if there was anything useful of another output signals such as GPCTR_SOURCE and GPCTR_GATE. For GPCTR_OUT I have used NI Visual Basic examples with components which work well. But I could not figure out how to program GPCTR_SOURCE and GPCTR_GATE or PFI signals with Visual Basic. I could use either components or DAQ functions but I could not find example.
Greetings,
Unfortunately, the other GPCTR lines (source and gate), when used in a counter context, are for input only. You may want to consider adding a counter (NI-TIO) board to your system:
PCI-6601
PCI-6602
Good luck with your application.
Spencer S. -
How do I generate two finite pulse trains using counters on PXI-6251
I'm trying to use Counter 0 and Counter 1 on the PXI-6251 to generate two finite pulse trains. But, I get this error: "The specified resource is reserved. The operation could not be completed as specified." See attached example.
Inside the disabled box is what I'd like to run on both counters. I stripped things down to creating the task, starting, and stopping. I then started to add things to see what my problem was. The timing VI seems to be what causes me issues but I don't know why.
My end objective is two identical pulse trains with one delayed by 5us, which I figured would be easy to do in the initial delay. I tried both in a single task and as separate tasks with no avail.
Attachments:
2_counter_outputs.vi 32 KBHi SirMutt,
Creating a finite pulse train requires
two counters. What’s really happening is that one counter is creating a
continuous pulse train while the other counter applies a finite pulse to “window”
the pulse.
What you want to do is correlated DIO. I’ve
done a search on our website for “correlated DIO” and have come up with a few
resources. Hopefully that will help you get started.
Digital Output and Pulse Generation
Performing Correlated Digital IO with an M Series Device in LabVIEW
M Series Hardware-Time DIO with Counter Clock Generation
Mark E.
Precision DC Product Support Engineer
National Instruments
Digital Multimeters (DMMs) and LCR Meters
Programmable Power Supplies and Source Measure Units -
How do you use the counters on board
I am involved in the development of a LabVIEW VI for the acquisition and processing of signals generated by a chip under test; my application provides two signals having the waveforms sketched in the attached figure.
With reference to this figure, I should generate a digital pulse just after a pulse on signal 1, also in case of no pulses on signal 2.
I am using the board PCI 6110 with LabVIEW 6i: I tryed to use the counters implemented on the board to generate my signal. My idea is to count the pulses of signal 1 with a counter and, if it is possible, to reset the counter on a rising edge of the signal 2. By so doing, when the counter assumes the value “2”, it must generate an impulse. Unfortunately I have not su
cceeded to implement this procedure.
Please, could you suggest me how to implement this solution, or, if this is not possible, any other procedure to accomplish the required task?
Thank you very much for your attention.
Attachments:
figure.jpg 17 KBHello Gian,
I've tried to think of a method to implement this for a while, but the one fundamental obstacle I keep coming across is that it seems the system must have a deterministic output. (It has to identify the gaps and generate the pulse while on the fly.) It is easy to acquire the two signals and even determining when the gaps occur. The problem is getting your software to recognize this and generate the output fast enough. You could possibly do this with a LabVIEW RT system.
On the other hand, I have thought of a way you could do this with a 660x counter/timer board using quadrature encoder position measurement mode. The problem with the 6110 is that it's counter/timers do not support this mode. With the 660x board in encoder position measurement m
ode, you can wire signal 1 to the source (which increments the counter) and signal 2 to the z-index (which resets the counter to a specified value). You would have this specified value set to be 2 less than the terminal count. If you recieved two signal 1 pulses without any signal 2 pulses, the counter would reach terminal count which triggers a short pulse to be generated on the output and this could be your output signal.
If you do decide to go this route, our technical support can assist you further with this after you have the hardware.
I hope this helps.
Russell
Applications Engineer
National Instruments
http://www.ni.com/support -
Hello!
My problem appeared when I tried to update my code from Traditional NI-DAQ Legacy to DAQmx.
I am using 2 counters (counter 5 and counter 7) from PCI-6602, to generate pulse train, and also the Digital I/O lines of the port 0 (the lines form 0 to 7). What I do in my application is that I am starting to generate the pulse train on the output of the 2 counters, and after that I am playing with the state of the digital lines.
In traditional there was no problem using the counters and the digital lines in the same time, everything was going perfectly, but in DAQmx this is not possible.
What happens: I start to generate pulse train on the output of the counters, no errors encountered, but when I try to modify the state of one line of the digital port the generation of the pulse train is stopped. This is happening when I start the task associated to the digital port.
My question is: it is possible to create a channel on the digital lines without altered the channels created for the counters?
Another thing what I manage to see using the "Measurement & Automation Explorer" and Test panels for PCI-6602, basically is the same thing, I generate pulse train on the output of the counter 7 and try to start a task on the digital line, but I get one error :
"Error -200022 occurred at Test Panel
Possible Reason(s):
Measurements: Resource requested by this task has already been reserved by a different task.
Device: Dev4
Terminal: PFI8"
Instead if I use the counter 0 or counter 1 to generate pulse train I don't encounter the same problem.
Which resources are used by the counters 2 to 7 from the PCI-6602 board and the counters 0 and 1 do not use?
Thank in advance for any replies!
Ciprian
Solved!
Go to Solution.Hello Jordan, thank you for your reply.
I am sorry but I can not see or run your example, I don't use LabView, I use Visual C++ for developing.
Here is the code for generating the pulse train:
GeneratePulseTrain(unsigned long ulCount1, unsigned long ulCount2)
short nStatus = 0;
nStatus = DAQmxCreateTask("",&m_taskHandle);
nStatus = DAQmxCreateCOPulseChanTicks (m_taskHandle, "Dev4/count5", "", NULL, DAQmx_Val_Low, 0.0, ulCount1,ulCount2);
if( bTriggerMode == true) // if hardware trigger is enabled
nStatus = DAQmxSetTrigAttribute (m_taskHandle, DAQmx_ArmStartTrig_Type, DAQmx_Val_DigEdge);
nStatus = DAQmxSetTrigAttribute (m_taskHandle, DAQmx_DigEdge_ArmStartTrig_Edge, DAQmx_Val_Rising);
nStatus = DAQmxSetTrigAttribute (m_taskHandle, DAQmx_DigEdge_ArmStartTrig_Src,"Dev4/PFI17" );
//set the internal timebase
nStatus = DAQmxSetCOCtrTimebaseSrc(m_taskHandle,"Dev4/count5","20MHzTimeBase" );
nStatus = DAQmxStartTask(m_taskHandle);
return nStatus;
And the code where I try to set the digital line:
SetChannelState(short nState)
short nStatus = 0;
uInt8 wrtBuf0[1]={0};
nStatus = DAQmxCreateTask("",&m_taskHandle);
// Configure line as output
nStatus = DAQmxCreateDOChan (m_taskHandle, "Dev4/port0/line0", "", DAQmx_Val_ChanPerLine);
nStatus = DAQmxStartTask(m_taskHandle);
wrtBuf0[0] = nState;
nStatus =DAQmxWriteDigitalLines (m_taskHandle, 1, 0, 0, DAQmx_Val_GroupByScanNumber , wrtBuf0, NULL, NULL);
nStatus = DAQmxWaitUntilTaskDone(m_taskHandle,10);
nStatus = DAQmxStopTask(m_taskHandle);
nStatus = DAQmxClearTask(m_taskHandle);
m_taskHandle = 0;
return nStatus; -
At irregular occasions I need to grab counts from several counters, and buffering the counts must be done simultaneously for all counters. I'm modeling my approach after zone.ni.com/devzone/cda/tut/p/id/5404 which someone kindly pointed out in an earlier thread. However, that example only uses one counter, and you can't test the synchronization with only one counter, so I am using two counters configured the same way, and they're wired to a single benchtop signal generator (for example at 300 kHz).
What I want to do, I can test in a loop with a somewhat random wait in it. I want to drive a hardware digital output line high for a few ms and then low again. The hardware line is physically connected to terminals for my timing vi's Sample Clock Source and so will cause them to buffer their counts for later reading. After I pulse this line, when I know new good buffered counts await me, I want to read both my counters. If their bufferings are simultaneous, then each counter will have counted the same number of additional counts since the last loop iteration, which I can check by subtracting the last value sitting in a shift register and then subtracting the two "additional counts" values and displaying this difference as "Diff". It should always be 0, or occasionally +1 followed immediately by -1, or else the reverse, because buffering and a count could happen practically at the same moment.
When I do this using a flat sequence to control the relative timing of these steps, so the read happens after the pulse, the counters often time out and everything dies. The lengths of time before, during, and after the pulse, and the timeout value for the read vi, and the size of the buffer and various other things, don't seem to change this, even if I make things so long I could do the counting myself holding a clipboard as my buffer. I've attached AfterPulse.vi to illustrate this. If I get 3 or 10 or so iterations before it dies, I observe Diff = 0; at least that much is good.
When I use two flat sequences running in parallel inside my test loop, one to control the pulse timing, and the other to read the counters and do things with their results, it seems to work. In fact, Diff is always 0 or very occasionally the +/- 1 sequence. But in this case there is nothing controlling the relative timing such that the counters only get read after the pulse fires, though the results seem to show that this is true. I think the reads should be indeterminate with respect to the pulses, which would be unreliable. I don't know why it's working and can't expect it to work in other environments, can I? Moreover, if I set some of the pulse timing numbers to 1 or 2 or 5 ms, timeouts start happening again, too. So I think I have a workaround that I don't understand, shouldn't work, and shouldn't be trusted. See SeparateSequence.vi for this one.
I also tried other versions of the well-defined, single sequence vi, moving the counter reads to different sequence frames so that they occur with the Sample Clock Source's rising edge, or while it is high, or with the falling edge, and they also often time out. I'll post these if anyone likes but can't post now due to the attachment limit.
Here's an odd, unexpected observation: I have to sequence the reads of the counters to occur before I use the results I read, or else many of the cycles of this combine a new count from one counter with the one-back count from the other counter, and Diff takes on values like the number of counts in a loop. I though the dataflow principle would dictate that current values would get used, but apparently not so. Sequencing the calculations to happen after the reads fixes this. Any idea why?
So, why am I not succeeding in taking proper control of the sequence of these events?
Thanks!!!
Attachments:
AfterPulse.vi 51 KB
InSeparateSequence.vi 49 KBKevin, thanks for all the work.
>Have you run with the little execution highlighting lightbulb on? -Yes. In versions of this where there is no enforced timing between the counter and the digital line, and there's a delay inserted before the digital line, it works. There are nearly simultaneous starts on two tracks. Execution proceeds directly along the task wire to the counter. Meanwhile, the execution along the task wire to the digital high gets delayed. Then, when the digital high fires, the counter completes its task, and execution proceeds downstream from the counter. Note, I do have to set the timeout on the counter longer, because the vi runs so slowly when it's painting its progress along the wires. If there is any timing relationship enforced between the counter and the digital transition, it doesn't work. It appears to me that to read a counter, you have to ask it for a result, then drive the line high, and then receive the result, and execution inside the counter has to be ongoing during the rising line edge.
>from what I remember, there isn't much to it. There really aren't many candidate places for trouble. A pulse is generated with DIO, then a single sample is read from each counter. -Yup, you got it. This should be trivial.
>A timeout means either that the pulse isn't generated or that the counter tasks don't receive it. - Or it could mean that the counter task must be in the middle of executing when the rising edge of the pulse arrives. Certainly the highlighted execution indicates that. Making a broken vi run by cutting the error wires that sequence the counter read relative to the pulse also seems to support that.
>Have you verified that the digital pulse happens using a scope? -Verified in some versions by running another loop watching a digital input, and lighting an indicator, or recording how many times the line goes high, etc. Also, in your vi, with highlighting, if I delete the error wire from the last digital output to the first counter to allow parallel execution, I see the counter execution start before the rising edge, and complete when the line high vi executes. Also, if I use separate loops to drive the line high and to read the counter, it works (see TwoLoops.vi or see the screenshot of the block diagram attached below so you don't need a LV box). I could go sign out a scope, but think it's obvious the line is pulsing given that all these things work.
>Wait! I think that's it! If I recall correctly, you're generating the digital pulse on port0/line0... On a 6259, the lines of port 0 are only for correlated DIO and do not map to PFI. -But I'm not using internal connections, I actually physically wired P0L1 (pin 66) to PFI0 (pin 73). It was port0/line1, by the way. And when running some of these vi's, I also physically jumper this connection to port0/line2 as an analog input to watch it. And, again, the pulse does cause the counter to operate, so it clearly connects - it just doesn't operate the way I think it is described operating.
For what it's worth, there's another mystery. Some of the docs seem to say that the pulse has to be applied to the counter gate terminal, rather than to the line associated with the sample clock source on the timing vi. I have tried combinations of counter gate and or sample clock source and concluded it seems like the sample clock source is the terminal that matters, and it's what I'm using lately, but for example the document I cited, "Buffered Event Counting", from last September, says "It uses both the source and gate of a counter for its operation. The active edges on the gate of a counter is used to latch the current count register value in a hardware register which is then transferred via Direct Memory Access...". I may go a round of trying those combinations with the latest vi's we've discussed.
Attachments:
NestedSequences.png 26 KB -
Hi
I ma using 6070E daq. I am generating a infinite pulse train using one of the counters. I want to generate another pulse train which should 90 degress phase shifted with respect to the previsously generated pulse. How to implement this using the counters in the DAQ card.Hi Gopal,
1) yes the frequency generator is programmable. You have 2 timbebases (10MHz and 100kHz) and you can divide down by any integer between 1-16. Those are the only frequencies you can use.
2) The way counters work is that you can apply a gate signal to the counter which will cutoff the output. Therefore, you can have a second counter generating a pulse train of an equivalent frequency to the frequency generator (fout) but you don't want it to start immediately. You want it to start only after a short delay (equivalent to a 90d phase). Therefore, you need to "gate" or prevent the output on this counter for that small delay period of time. The way you can do this is by using a second counter to create a delayed pulse. You would
connect the output of that counter to the gate of your pulse train function. That way, during the delay period of the pulse, you won't be outputing your pulse train yet. When the pulse (high-time) of your pulse reaches the gate, then your pulse train will start generating its pulse train (which is consequently delayed by the amount of delay used in the single delayed pulse counter). Since you don't want your pulse to go back low, you will have to turn off or clear your pulse counter while it is high. That way the signal on the gate will remain high forever.
Your better solution is to use a PCI-660x card to perform this action. You will have more counters which will give you a greater range of frequencies to choose from and you will have more accurate timing of the signals.
Anyway, hope that clears things up. Have a good day.
Ron -
How do I output a finite pulse train through multiple counters?
Hello,
I have used LabView examples to create a VI to use with my TIO 6602 that generates a finite pulse train with varying duty cycle, frequency, number of pulse, and initial delay. I can also have it output the pulses through multiple counter channels, but all the channels have the same delay, and are output at the same time. I need each channel to have a specific delay from the first one.
In my VI, I use DAQmx to create a retriggerable finite pulse train by gating a counter with another counter. I have all the neccessary controls over the pulse train, but I can not seem to find an easy way to just copy this waveform and output delayed versions of it to other channels. The delay is very important because these signals will be used to drive ultrasound transducers in a linear array, and for the waveforms to focus at one point, the signal driving the transducers with a shorter distance from the focal point need a larger delay, so that the same waveform arrives from each transducer at the same time.
Any help with how I might do this would be much appreciated.
Thanks!Hey Sneaky,
Here's a screenshot of the code I put together on how to use multiple counters. Also, take a look here for more information on how to sync multiple counters.
Message Edited by Knights Who Say NI on 02-02-2009 10:36 AM
Message Edited by Knights Who Say NI on 02-02-2009 10:36 AM
Message Edited by Knights Who Say NI on 02-02-2009 10:38 AM
-John Sullivan
Analog Engineer
Attachments:
4xcount.jpg 67 KB -
Adjust Counter Delay on the fly using two Counters
Hi,
I'm using the technique described here by JohnP to implement an on the fly delayed output of a hardware counter relative to it's trigger.
http://forums.ni.com/t5/Multifunction-DAQ/Synching-AO-and-Counter-Output-arming-and-triggering-seque...
My system generates a hardware buffered regenerative analog output. A continuous synch pulse is generated using Cntr0 on the same PCI-6221 and is triggered off of the AO.StartTrigger in order to synchronize the Cntr0 Pulse with each generation of the AO wavefrom. Then Cntr1 is configured in retriggerable single sample high/low time mode and triggered off of the Cntr0.InternalOuput. By changing the low time of Cntr1 I can effectively implement an adjustable on the fly delay on the ouput of Cntr1 relative to Cntr0 and hence relative to the AO waveform.
The technique works great for rational values of drive period, (i.e. 1.258 s), but when an irrational waveform period is commanded such as (0.59405940594059405940594059405941 s) the Cntr1 delayed pulse drifts relative to Cntr0. Meaning if you start with a 0 second delay between the two counters, the output pulses are initially aligned but then Cntr1's output will rapidly drift such that the two counter outputs are no longer synchronized.
Clearly there is a rounding error occuring but I can't seem to correct it. I changed the Cntr1 high/low mode from time in seconds to clock ticks thinking I'd have better resolution but still see the same drift with irrational drive periods. I also suspect that by calling the Cntr1 property Cntr.RdyForNewVal in a loop the hardware determinism of my system is compromised.
Our current solution is to simply coherce the user commanded AO drive period to rational values.
I'm mainly wondering if this problem can be corrected or if it's just a limitation of the method using two counters to create an on the fly counter output delay.
Thanks,
SteveJohn,
I'm measuring the drift of the output signals (AO and Cntr1) on a daq board scanning at 5000 scans/s.
The information you provided is helpful, I wasn't aware of the divide-down on the internal timebases. Yes, I am specifying the frequency directly to Cntr0 so this may be coerced differently than the AO.
Where does one find these specifics on the board and various clocks?
I've attached some sample code that may be of help to future users of this technique. The sample code outputs a continuous regenerative buffered Analog Output waveform (board hardware timed). Cntr1 is then configured in Frequency mode and triggers off of the AO.StartTrigger in order to synch the two signals. Then Cntr1 is configured in High/Low mode and triggered off of the Cntr0.InternalOutput. By changing the Cntr1 low time, I'm able to get an on the fly delayed output of Cntr1 relative to Cntr0 and hence the AO.
If you have a daq board and you wire the AO and Cntr1 output signals into two analog input signals, you can see the drift when using irrational frequencies. The sample code I provided only performs the output, so to see the signals you can simply create a continuous acquisition task in Max at 5Khz.
Thanks for you time and support.
Attachments:
Delayed Counter Pulse.zip 137 KB -
How to make load simulator using labview 2010
i want to ask how to make load simulator using labview?
Solved!
Go to Solution.what have you tried so far? and exactly what is it your tying to do?
Please remember to accept any solutions and give kudos, Thanks
LV 8.6.1, LV2010,LV2011SP1, FPGA, Win7 -
How do you create a finite pulse train using a FP-CTR-502?
I have recently replaced my FP-PG-522 module with a FP-CTR-502 module, to achieve higher output frequencies (FP-PG-522 max output freq is 5kHz, wheras the FP-CTR-502 max output freq is 16 kHz).
I need to be able to generate a finite pulse train. Has anybody created a finite pulse train using a FP-CTR-502 module before? I have started to look into it, but my ideas so far have been complicated (compared to doing it in a PG module).
Any tips on this would be much appreciated.
Christopher Farmer
Certified LabVIEW Architect
Certified TestStand Developer
http://wiredinsoftware.com.au
Solved!
Go to Solution.I can answer this question myself!
The answer is in the *OLD* version (July 2000) of the operator's manual for the FP-CTR-502. For some reason, this has been removed from the latest version (June 2003).
See page 11 of this link for more information:
http://www.ni.com/pdf/manuals/322660a.pdf
Christopher Farmer
Certified LabVIEW Architect
Certified TestStand Developer
http://wiredinsoftware.com.au -
Can i use 6025E card on Dos using Turbo C?
I need to include 6025E card with running program based on turbo C.(Most of the code reletaed to interrupt coming from 4 ports).Can i use NI-DAQ with turbo C"?
Ezi,
You cannot use the 6025E in DOS, because the latest version of nidaq that support DOS is 4.8, and the first version of nidaq that supports the board is 6.5. Thus, they don't match at all. You have to use windows OS, with a C compiler for that environment.
Hope this information is helpful.
L Aguila
Applications Engineer
National Instruments -
How can i generate variable pulse waveform using PWM outputs of 7344.
Hi
I want to generate a pulse waveform using the pwm outputs of 7344. How can i very the frequency of the PWM programatically.If you are programming in LabVIEW, you can use the Configure PWM Output VI to set up the frequency of the pulse train. If you are in any other language, you can use the NI-Motion API and call the flex_configure_pwm_output function to achieve the same result. Please refer to the NI-Motion C reference help that gets installed with the NI-Motion 6.0 driver or follow this link:
http://digital.ni.com/manuals.nsf/websearch/92003B670CC3CB3F862567C800755B95?OpenDocument&node=132090_US
for more information on this function. -
Ramping a pulse signal using PCI-6602 card
I'm controlling a stepper motor and need a continuous pulse output with variable frequency. I need to accelerate and decelerate teh motor (It can't start immediately at a high frequency but needs to be ramped up to it). I can't have any hiccups in the signal or the motor can stall. It seemed I had my own ramp program written (which gradually increased the frequency value sent to the counter) to solve this problem, but when I switched to Office2000 I started getting hiccups in my signal. I also have a PCI 1200 card and could use A/O but I think using the counter signals would be better. If I'm wrong let me know. Once I have the motor up to speed I am reading in a pulse signal to analyze with FFT.
thanks for y
our help.A few thoughts & musings, hope some of them are useful:
1. The sequence for setting a new frequency should be to first load up the new pulse specs (use 1 & 2, not 3 & 4), then issue the "switch cycle" command to 'Counter Control.vi' You can look at NI's example program called 'Pulse Width Modulator' to verify syntax.
2. If your frequencies are low enough and your loop time is fast enough, you may be trying to update the pulse specs before the previous specs have completed a full cycle. This has traditionally been a no-no, though I'm not 100% sure that it remains one with the latest NI-DAQ drivers.
3. No ideas about the possible interaction with MS Windows and/or Office 2000. Haven't used either.
4. (My own latest installment in a multi-year running gripe at NI): Wh
en oh when will we be granted the ability to perform buffered counter OUTPUT operations? Just as in the analog world, one can acquire a signal with AI and then reproduce it with AO, it would be REALLY REALLY handy in the counter world to measure with buffered semi-periods and then reproduce the same pulse train with a buffered output.
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