Help with "DAC Configure for Quadrature Mode.vi" in "ni5640R Frequency Translation" Example

Question

Hi there:
I am also using the the NI PCI-5640R and I've been "studying" the
program: "Frequency Translation", my intention is to modify it and
produce a  closed-loop between I and O. 
I am also interested in transferring what i am reading through the
input port, directly to the output port but filtered AND with a
phase-shift (final Objective: Q-Control). 
I need to visualize the signal in the HOST, so I need both FIFOS (DMA
FIFO and  Local FIFO), and the "Quadrature Mode DAC Configure"
I would like to know:
1. How can I directly transfer the data acquired through the ADC port
into the DAC?  (it is unclear due to the Event structure in the
"Frequency Translation" example)
2.
How can I configure the "Quadrature Mode DAC Configure.vi" for it to
bandpass-filter the signal comming from the ADC at a given frequency
and BW, specified by the user in the HOST? I have read that it is possible to filter a signal comming to the DAC using DUCs (Digital Upconverters) Does anyone has more info about this topic?
3. Is it possible to
configure the "Quadrature Mode DAC Configure.vi" to produce a
phase-shifted signal (phase shift also specified by user in the host)
I've
been working for almost 2 months trying to program the 5640R, doing
examples, and modifying them.  After playing with different examples
I've come up to the conclusion that the "Frequency Translation" example
is the one that best-suites my application.  My problem now is that I
AM LOST because i need more information regarding the configuration
parameters of ALL the different VI's inside the NI-5640R VI Tree  to
exploit them correctly, specially the "Quadrature Mode DAC
Configure.vi".
Can anyone please help me?
Cheers...Antonio

Answer 1

Hello again:
Jerry:
1. I referred to the Event structure, but in the HOST, but now, with your commentary and Philippe's explanation i've undestood better the concept.
2. Regarding the filtering, I read the datasheet of the AD6654 (DAC from "Analog Devices" which is part of the n5640r) and in pages 36 and 37, it explains with an example, the possibility of designing a Bandpass CIC Filter by changing the interpolation (or decimation) factor of the DUC (or DDC).  The filter can't be fully customized (the rejection and passband are limited to an "Alias rejection Table" in page 36), but it could fit the application to filter certain frequencies.
I also tryed what you guys suggested, meaning: I designed a simple digital bandpass butterworth IIR filter in the FPGA target inside a 3rd SCTL with a faster clock (i.e. "Top level timing source") and using a 2nd Local FIFO.  The filter was done with FPGA discrete delays (z^-n) departing from a "differences equation" [y(n) = x(n-1)+x(n)+0.9996858*y(n-1)].  But I have problems with the 0.99... constant which is always rounded to 1 (check the pic).  I changed the variable's type and digits of precision, but it still rounds up to 1 Any suggestions?
3. I was thinking as well of shifting the phase (as Jerry said) by configurating the NCO in the DAC.  Again, more information is given in AD6654's datasheet  (page 35).  I will quote the info:
"The phase offset register can be written with a value that is added as an offset to the phase accumulator of the NCO.  This 16 bit register is interpreted as 16-bit unregistered integer.  A 0x0000 in this register corresponds to a 0 radian offset and a 0xFFF corresponds to an offset of 2pi*(1 -  1/2^16) radians.  This register allows multiple NCOs (multiple channels) to be sinchronized to produce complex sinusoids with a known steady phase difference:"
Any ideas of how to program this register inside the "ni5640r ADC Configure NCO" to have a fixed phase offset of 90º?
Thanx in advance for your replies
'till the next post...Antonio
Attachments:
Digital IIR.JPG ‏122 KB