High Throughput Divide Inverted?

I am trying to optimize a large FPGA VI and was doing some simple tests to determine FPGA usage and timing for some high use items. I was comparing the high throughput divide with the normal one. I am using a cRIO-9066. What I found was that the inputs to the high throughput divide, in this case, appear to be reversed.
The equivalent normal divide works as expected, although it does take more resources and time. Has anyone else seen this? If so, is there a workaround?

Forgot to add my versions. I am using a fully patched 2014SP1 stack (LabVIEW, FPGA, RIO).
I have also since tested the high throughput divide in pipelined mode, and it has the same issue there, as well.

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    Solved!
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    Attachments:
    highthroughputdivisionormultiply.png ‏31 KB

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    Attachments:
    highthroughputdivisionormultiply_2.png ‏52 KB
    highthroughputdivideIssue.vi ‏21 KB

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