FPGA quick questions: High Throughput Division vs. Multiplication Implementation (rounding?)

Hi all,
I'm trying to implement a simple routine where I divide a FXP by the number 7 in FPGA. I wanted to use the high throughput division but it seems to only round to the nearest integer although the output is capable of representing fractions. Alternatively, I could multiply my number by 1/7 using the high throughput multiplication and I get what I want. I'm not too familiar with FXP arithmetic. Without fully understanding the problem, I at least have a solution which is to use the multiplication. I'd just like to know a little more. Can anyone please shine some insight on why the division rounds even though it can handle fractions?
Thanks for your help
Jeffrey Lee
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Attachments:
highthroughputdivisionormultiply.png ‏31 KB

Thanks for the suggestions. I recreated this and indeed was able to get the correct results! So what happened?
This may blow your minds, but there is something inherently wrong with my x/y indicator. I have it on "adapt to source". I created another supposedly identical indicator ("x/y 2") off the same wire and get the correct result with that indicator. This seems like some kind of bug but it worries me because I should have never run into it.
I've attached a screenshot of the code in action as well as the VI (i'm using 2011)
Thanks
Jeffrey Lee
Attachments:
highthroughputdivisionormultiply_2.png ‏52 KB
highthroughputdivideIssue.vi ‏21 KB

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Hello,
i am just trying to unterstand what advandages the High Troughput Math Funtions have. So i have to ask some Questions.
I always talk about beeing inside a SCTL.
1. In the Image you can see four Add Functions. One with U32 which should use more Ressouces than the one with the U16Datatype which uses mor than the U8. But does my FXP High Througput Math Function use less Ressources than the U8 Version?
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I don't see a big rush to answer this, so I'll give it a shot:
1. The HT version uses less resources, but only because it is configured with the smallest data types. You should get exactly the same results with the same data types and an Add function. The only difference with the HT version is the ability to specify an output register, and the handshaking signals that account for that delay. IF the add is implemented in a DSP48, the integrated register can result in better timing, but in practice it is usually equivalent to an Add function followed by a feedback node.
2. The actual delay through an add is proportional to the number of bits, where the critical path is the sequentially computed carry chain. So you could run the last one at the highest clock rate. The FPGA has dedicated fast carry logic, so the difference isn't too significant.
3. The first one will be VERY slightly smaller and faster, just because you're computing one extra output bit on the second one.
4. I would expect the speed to depend only on the number of DSP48s used, so the last 3 should be similar. You'd be likely to see different results in practice, though, due to routing differing numbers of bits to registers for the indicators. This assumes you're not taking advantage of any of the pipelining configuration options in the HT Multiply. Those options, and the associated handshaking signals, are really what differentiates the HT versions from the regular numeric functions. They allow you to achieve higher clock rates and throughput at the expense of latency (ie, it will take more clock cycles to produce a valid result but you can get more data through the function in a given amount of time).
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Hi pablosan,
If I understood correctly, you want to generate a sine wave with a high throughput block in Labview FPGA.
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You might find this link from the help information: Using the High Throughput Math Functions
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1. I could order my MBP from the computer store at my university. Do you guys think that will get me the newest possible MBP or will they maybe get me one that they have had in stock for ages? I really don't want to get stuck with an outdated logic board and/or battery. Is it safest just to order directly from the site?
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I would assume that in following their "mission" of creating beautifully designed computers, Apple also wants to have a really silent one. Now I'm all for a quiet machine, but I feel as though if fans were on either (a) all the time or (b) when the CPU reaches the high 50s lots of people would be happier.
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More likely there are a lot of people around here who think they are experts. As the remark goes, "An 'expert' derives from ex, meaning 'has been', and spert, meaning 'drip under pressure.'"
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Hi
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FPGA quick questions: High Throughput Division vs. Multiplication Implementation (rounding?)

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