How to simulate a pll circuit with NI MULTISIM

I want to simulate a PLL circuit with Multisim 13.0 before building it on the real NI ELVIS 2 breadboard. I want to see what results I should be expecting first, but I couldn't find a 74HC4046 chip in the Multisim software. Does anyone know how I can find the 74hc4046 chip in that software?

Hi there,
When a component is not available in the Multisim Database, you can try to find a SPICE model for the component and then use the Component Wizard (Tools menu) to create a custom component. Click here to learn more about component creation.
Usually, SPICE models can be found in the manufacturer's website. I did a quick search but could not find a model for the 74HC4046.
In Multisim, there is a generic PLL that you could use. It can be found in the Mixed Group, MIXED_VIRTUAL family.
Regards,
Fernando D.
National Instruments

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Please tell me in detail which wire should go to which number (eg. A1, B2, C4 etc...).
I am in need of big help here. I don't know what else should be done to get this correct.
I have to build this PLL circuit and choose any 3 N (integer) of the N-divider. Then I have to observe the input signal Sig_in and the output signal VCO_out for each N. The result should be that the output frequency is N+1 times bigger than that of the frequency set by ELVIS (function generator), if I have understood the instructions correctly. I attached my results. The output signal looks weird, right? When I set N as 1, the output signal gets messed up :/ I tried for N= 4 and 8, the waveform looked just the same as when N=1. What should I do? By the way, where should I connect the 5th pin of IC 85 (A=B) to? In the diagram it just shows a short line not connecting to anything.
I took 4 pictures of different angles so you can see better.
http://www.flickr.com/photos/98820721@N04/11870437296/sizes/o/in/photostream/
http://www.flickr.com/photos/98820721@N04/11870033074/sizes/h/in/photostream/
http://www.flickr.com/photos/98820721@N04/11870445586/sizes/k/in/photostream/
http://www.flickr.com/photos/98820721@N04/11869882813/sizes/k/in/photostream/

Please keep everything in this thread. No one is going to try to debug the photos of your wiring shown in the other thread.
Do you understand how the 4046 works? When you have both R1 and R2 connected you have a limited range of frequencies from the VCO. Page 5 of the Fairchild datasheet for the 74HC4046 shows fmax/fmin no larger than 7.5 to 9.5 regardless of the ratio of R2/R1, depending on the value of Vcc. For R2 = R1 fmax/fmin ~ 1.7. So the circuit you have cannot possibly work for more than one value of N! Well, maybe it would work for a few closely spaced values at the high end of the range.
Study the datasheets. Decide what specifications you actually want to meet. Calculate the minimum and maximum frequencies at the VCO output. See if you can select values for the VCO and filter passive components which might work. Then try it.
Also, look at the logic design. I doubt it does what you expect. Try drawing a timing diagram manually and look at the A>B and A<B outputs.
When you are troubleshooting a PLL circuit, it is useful to look at the output of the phase detector or filter. That will tell you if it is trying to force the VCO to one extreme or the other. It will also tell you whether the signal is steady, oscillating periodically, or moving somewhat randomly. Each of those can be a clue as to what is going on. Also look at the A>B and A<B outputs of the comparator.
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vlsi,
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How to simulate a pll circuit with NI MULTISIM

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