I am trying to use generate code in signal express to import into labview.

I get this error when i try to generate code in signal express to export to labview . I have tries the error suggestions but I am still having problems. any help would be appreciated
The version of LabVIEW you are generating code into does not contain all the necessary SignalExpress support files. Make sure you launch the version of LabVIEW with SignalExpress support installed before generating code from SignalExpress. If you want to generate code into more than one version of LabVIEW, uninstall SignalExpress and all versions of LabVIEW except the earliest. Install SignalExpress, then install any other versions of LabVIEW. Copy the files from the vi.lib\express\SignalExpress directory of the earliest installed version of LabVIEW into the same sub-directory location of any other version of LabVIEW in which you want to include support for code generation.

Typically, this problem is repaired by following the directions on the error message. Since it was not, can you please give us more information so we can start determining the cause?
What version or versions of LabVIEW do you have installed? What version or versions of SignalExpress do you have installed? Could you post a file with a listing of the files in <vi.lib>\express\SignalExpress for the version of LabVIEW you are trying to use. You can either post a screenshot (in PNG or GIF format) of the directory dialog or use the command prompt to generate a list to a file (preferred). To generate a list with the command prompt, do the following:
Launch the command prompt from the start menu — Start»Programs»Accessories»Command Prompt
Navigate to the drive you have LabVIEW installed on ( usually C: ) — C:
Change directory to the appropriate LabVIEW directory — cd "\Program Files\National Instruments\LabVIEW 8.2\vi.lib\express\SignalExpress". Change the LabVIEW version to the one you actually are using. Do a directory listing and redirect the output to a file — dir > filename.txt. You can use any full path for the filename.txt. If you specify a simple name, it will end up in the current directory.
Please post your project. Verify that you are using the version of LabVIEW you think you are by launching it before you start code generation.
Thanks for your patience.
Message Edited by DFGray on 08-28-2008 08:23 AM
Message Edited by DFGray on 08-28-2008 08:24 AM
This account is no longer active. Contact ShadesOfGray for current posts and information.

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==============================
module andtwobits (xx, yy, zz);
input xx, yy;
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end
endmodule
==============================
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==============================================
library ieee;
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==============================================
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Please find the attachment for the all files.
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Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
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NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
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Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
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endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
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        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
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         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
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            in2 => in2,
            out1 => out1
END RTL;
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NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
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XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

How do I view movies using apple tv that have been imported into iMovie?

I am trying to view movies using a second generation AppleTV that I imported into my computer from my video camera using iMovie. I tried importing them into iTunes after importing them with iMovie but it creates a second copy of the movie and I don't have room on my hard drive. Can I view them on my Apple TV without importing them into iTunes?

Welcome to the Apple Community.
iMovie is an editing application, you import raw footage, edit it, export it and if you don't have a lot of room trash the original files. It is not intended to be used for finished movies.
Video footage for editing needs to be in a different format than it does for delivery, delivery formats (m4v etc) are highly compressed and take up considerabally less room than footage in an editing format.

How to use wscompile to generate code using a WSDL file?

I am working with JAX-RPC of Java Web Service ver: 1.1. I am intrested in making the WSDL file first and generating Java code from the WSDL file. On the following link:
http://java.sun.com/webservices/docs/1.1/tutorial/doc/JAXRPC6.html#wp80094
it says that wscompile can generate code using a WSDL file..:
<quote>
Table 11-3 wscompile Options
-import : read a WSDL file, generate the service's RMI interface and a template of the class that implements the interface
</quote>
and the wscompile software says this:
<quote>
C:\>wscompile
-import : generate interfaces and value types only
</quote>
can anyone tell me how to generated Java code from a WSDL file. As in, make the WSDL file (e.g. using XMLSpy) and then use that WSDL generate Java code.
Thanks

I'm trying to generate code using wscompile under the struction in JAXRPC_Tutorial.pdf.
I issued the following command:
wscompile.sh -keep -gen:client -f:wsi -verbose config.xml
But I met with the following warning and I cann't find the produced java code, who know why? Thanks in advance!
warning: ignoring SOAP port "EmployeeDBPort": unrecognized transport
warning: Service "EmployeeDatabase" does not contain any usable ports
the config.xml file is:
<?xml version="1.0" encoding="UTF-8"?>
<configuration
xmlns="http://java.sun.com/xml/ns/jax-rpc/ri/config">
<wsdl name="EmployeeDBService"
location="EmployeeDB.wsdl"
packageName="com.sun.xml.rpc.xml.EmployeeDB">
</wsdl>
</configuration>

HowTo: Use package structure in generated code?

Hi,
I'm trying to find out if JCS is meeting my requirements for JSF development. So far it is pretty good, although the lack of support for new components is defeating the purpose of JSF for a great deal.
One of the most terrible things I encountered so far is the fact that I've been unable to get JCS to create a package structure to contain the generated code. In other words, I want JSC to generate the code in "src/com.foo.bar.my.application" instead of just the root of "src/" (where src/ means the source-folder of my project).
This is a real drawback.
Maybe I'm wrong, but in that case it's a plain bug because I can't get it to work.
Iwan

Admitedly, Creator does not yet offer much flexibility in terms of user-defined package structure. I know you won't like this, but here's a workaround/hack that almost gets to where you want to be.
First of all, the binding between jsp file and backing bean is defined by the relative positioning between the two files. A JSP file at the top level folder maps to a backing bean just under the assigned java package name (something like webapplicationxx). If you create a directory structure for your JSPs and create pages in them, Creator will create a corresponding package hierarchy for the backing beans.
So, one way to contrive a java package structure such as com.foo.bar is as follows (best to start with a new project):
1. Under the Web Pages folder, create a subfolder hierarchy "foo/bar".
3. Under the Java Sources folder, rename the top level package to 'com'.
4. You may now create Web pages in the foo/bar subfolder. You'll probably want to cut & paste the Resources directory into the foo/bar folder if you want to use stylesheets, etc. As the pages are created, notice that a com/foo/bar package structure is created under the Java Sources node where the backing beans are maintained.
One final note, due to a bug in Creator, renaming the package in step 3 does not properly update references to the old pacakge in SessionBean1.java. These will have to be manually changed in the editor. Also note that the ApplicationBean1 and SessionBean1 files must remain at under to top-level package.
We acknowledge this deficiency in Creator and are working to fix it in the next release.

I am trying to use generate code in signal express to import into labview.

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