ILA, How to qualify and trigger on a subset of signals?

Hello Vivado ILA users,
I am trying to verify a signal processing block that is too large to verify in simulation. Instead, I am using Vivado ILA to capture the data and writing out the data using the "write_hw_ila_data" command. Then I have a special script that converts the binary strings into a matlab readable format. It was a lot of effort to get all that working but now I am hitting a situation where the ILA no long meets timing. I could turn down the clock but I think the problem is how I am using the ILA.
The data in my block flows in a streaming fashion with a datavalid signal indicating when data is available. I only want to capture valid data so I have turned on the storage qualifier mode of the ILA. It seems that trigger/qualifier logic is being generated for all the data signals that I am capturing, not just the very few signals I use for trigger and qualification. I think this super wide trigger/qualifier logic is what causes ILA to miss timing.
Is there a way in Vivado ILA to select a different set of signals for triggering and qualification?
I remember this was part of the standard flow in old ISE Chipscope but I do not see how to do it in Vivado. I looked through UG908 and PG172. I should mention that my clock frequency is only 200MHz, very moderate for 7-Series parts.
I attach my add_ila.tcl script and then the long path of the timing report below.
#set ila_clock clk_BUFG
set ila_clock clk_IBUF_BUFG
#set_property mark_debug true [get_nets [list {uut/ola_out_dv}]]
#set_property mark_debug true [get_nets [list {uut/ola_dout_real[0]*}]]
#set_property mark_debug true [get_nets [list {uut/ola_dout_imag[0]*}]]
#set_property mark_debug true [get_nets [list {uut/ola_branch_out[*]}]]
create_debug_core ila1 ila
set_property C_DATA_DEPTH   4096 [get_debug_cores ila1]
set_property C_EN_STRG_QUAL true [get_debug_cores ila1]
set_property C_ADV_TRIGGER true [get_debug_cores ila1]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores ila1]
set_property TRIGGER_COMPARE_VALUE true [get_debug_cores ila1]
# Now find all the nets that are marked for debug.
set ila_nets [get_nets -hier -filter {MARK_DEBUG==1}]
set num_ila_nets [llength [get_nets [list $ila_nets]]]
set_property port_width 1 [get_debug_ports ila1/clk]
set_property port_width $num_ila_nets [get_debug_ports ila1/probe0]
connect_debug_port ila1/probe0 [lsort -dictionary [get_nets [list $ila_nets ]]]
get_nets [list $ila_nets]
connect_debug_port ila1/clk [get_nets [list $ila_clock ]]
write_debug_probes -force ./results/ila1.ltx
    SLICE_X4Y50          FDRE (Prop_fdre_C_Q)         0.456     5.666 r ila1/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[1]/Q
                         net (fo=73, routed)          0.859     6.525    ila1/inst/ila_core_inst/u_ila_regs/n_19_U_XSDB_SLAVE
    SLICE_X7Y50          LUT6 (Prop_lut6_I0_O)        0.124     6.649 f ila1/inst/ila_core_inst/u_ila_regs/current_state[6]_i_3/O
                         net (fo=5, routed)           0.804     7.454    ila1/inst/ila_core_inst/xsdb_memory_read_inst/I3
    SLICE_X7Y44          LUT6 (Prop_lut6_I2_O)        0.124     7.578 f ila1/inst/ila_core_inst/xsdb_memory_read_inst/current_state[4]_i_1/O
                         net (fo=3, routed)           0.823     8.401    ila1/inst/ila_core_inst/xsdb_memory_read_inst/next_state[4]
    SLICE_X7Y46          LUT6 (Prop_lut6_I4_O)        0.124     8.525 r ila1/inst/ila_core_inst/xsdb_memory_read_inst/curr_read_block[1]_i_2/O
                         net (fo=1, routed)           0.149     8.674    ila1/inst/ila_core_inst/xsdb_memory_read_inst/n_0_curr_read_block[1]_i_2
    SLICE_X7Y46          LUT6 (Prop_lut6_I1_O)        0.124     8.798 r ila1/inst/ila_core_inst/xsdb_memory_read_inst/curr_read_block[1]_i_1/O
                         net (fo=2, routed)           0.694     9.492    ila1/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/pwropt_1
    SLICE_X7Y49          LUT5 (Prop_lut5_I1_O)        0.124     9.616 r ila1/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_REGCEB_cooolgate_en_gate_21/O
                         net (fo=1, routed)           0.584    10.200    ila1/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_REGCEB_cooolgate_en_sig_1
    RAMB36_X0Y9          RAMB36E1                                     r ila1/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/REGCEB
-------------------------------------------------------------------    -------------------

Update: I recompiled my design with storage qualification turned off and the ILA still misses timing by half a nanosecond.
Then I compiled the design without any ILA installed and met timing by 2ns.
I remember using large ISE Chipscope cores at 300MHz in Virtex-5. Is there some funny business here? Do I need to constrain the ILA by some means other than the clock period constraint I put on my design?

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