Invalid Mapping with SIT for an outport inside a subsystem in a the simulink model.

Hello everybody,
I am trying to use SIT to target simulink models on a PXI target.
The simulink model contains a subsystem with an outport. I have created
a mapping between the signal coming out of that outport to a waveform
chart on the host VI. The mapping works fine when I run the model on
the local host but becomes invalid when I target the dll to a pxi
target.
I have been able to create a very simple simulink model and host VI
that is mimicking this problem. This model does
not do anything useful and is made to only demonstrate just this problem. I am attaching the model and the userinterface here.
Note:
I have already taken care of the fact that I can not use signal storate
reuse, block reduction and also cant use linked or linked+masked
subsystems. A testimony to this is the fact that I am able to create
mapping with other signals in the subsystem. Also outport is a virtual
block in simulink so I have created a testpoint on the signal going
into the outport to be able to probe it.
Any kind of suggestions would be appreciated.
Thanks and Regards,
Vicku.
Attachments:
files.zip ‏77 KB

You have two options to be able to probe this signal in the subsystem that should work fine for this small example you posted. Let me know if they also apply to your actual model.
You have the outport itself set as a test point currently in your subsystem block. Try setting the wire coming out of the subsystem outport as a test point and then rebuilding your dll. That should make the outport signal probable.
Instead of probing the actual outport, you could probe the signal in the subsystem that is wired into the outport. In the case of your example that would be using_subsystem/Subsystem/Sum1:1.
Hope this helps!
Message Edited by Jarrod S. on 08-23-2007 10:59 AM
Jarrod S.
National Instruments

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