Is an FPGA Host Interface a blocking shared resource?

Question

I'm curious to know if the FPGA Host Interface node is a shared resource. Meaning, if I have a Timed Loop on a LabVIEW Real-Time target (e.g. cRIO) that is reading and writing from the FPGA using the Host Interface. Will the determinism of that loop be adversley affected if I access other signls on the FPGA using the Host Interface in a separate loop (either a Timed loop or a normal while loop).
Said more tersely, is the FPGA Host Interface a shared resource that can cause a priority inversion if called from two seperate loops?
Thanks.
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Answer 1

Hi Southern_Cross
According to our documentation, you should be able to have more than one reference to the FPGA open at the same time ( as long as all the references access the same VI in the FPGA), and use them all in different places in your code from the same target. Since you can only have 1 main VI in the FPGA, accessing the reference of the FPGA behaves more like an I/O than like a non reentrant VI. 
Using Multiple FPGA VI References for the Same Target (FPGA Interface)   
As long as you are not writing the same variables in both loops (which could cause a race condition) you should be fine.
WenR