LabView SIT

I have 33 model parameters identified as global tunable parameters in SimuLink and upon creating the .dll file and opening it in LabView VI I get only 16 parameters. How do I get the 33 parameters seen by LabView after the conversion using SIT? Matlab version 2010a and LabView version 2010 with MS Visual Studio 2008.
Thanks

From my experience with SIT, LabVIEW likes to have a 'Test Point' on the signal in Simulink prior to creating the .dll made with Real-Time Workshop. To make a test point in Simulink, right-click on the signal line and go to properties. From there, you should see a checkbox for a Test Point. Check it and a graphic that looks like a golf ball and a tee will appear on your signal line. Then rebuild the .dll and they should show up in SIT for hooking onto.
Michael
-You can never have too much power...

Similar Messages

Not able to create OUT file with "nidll_vxworks" in Matlab for use with the LabVIEW SIT 2010 and a cRio 9073, sh.exe error

I am trying to compile an OUT file for my Simulink model using "nidll_vxworks" and run it using the Simulation Interface Toolkit for a cRIO 9073 . I am able to compile the DLL file using "nidll" and succesfully run the simulation using my PC as the host.
I already downloaded the "gccdist" and "vxworks61gccdist" folders and copied them to "c:" When I build the model in Sumulink I get the following error at the end of the process (at the same time windows tells me that "sh.exe" has stopped working). If it matters I am running Windows 7 64bits, but using Matlab 2009b 32bits and LabView 2010 32 bits. ANY HELP WILL BE APPRECIATED. "QofV" is the name of my Simulink model and I changed to "XXX" parts of the file path.
### Linking ...
rm -f "QofV.out" ctdt.c;nmppc QofV.o QofV_data.o rtGetInf.o rtGetNaN.o rt_logging.o rt_look.o rt_look1d.o rt_nonfinite.o nidll_main.o rt_sim.o ode8.o | tclsh c:/gccdist/WindRiver/vxworks-6.3/host/resource/hutils/tcl/munch.tcl -c ppc > ctdt.c
abnormal program termination
C:\Users\XXX\AppData\Local\Temp\make426012.sh: fork failed: no child processes [1]
make: *** [QofV.out] Error 1
### Real-Time Workshop build procedure for model: 'QofV' aborted due to an error.
>>
### Linking ...rm -f "QofV.out" ctdt.c;nmppc QofV.o QofV_data.o rtGetInf.o rtGetNaN.o rt_logging.o rt_look.o rt_look1d.o rt_nonfinite.o nidll_main.o rt_sim.o ode8.o | tclsh c:/gccdist/WindRiver/vxworks-6.3/host/resource/hutils/tcl/munch.tcl -c ppc > ctdt.c
abnormal program termination
C:\Users\XXX\AppData\Local\Temp\make426012.sh: fork failed: no child processes [1]make: *** [QofV.out] Error 1 ### Real-Time Workshop build procedure for model: 'QofV' aborted due to an error.>>
### Linking ...rm -f "QofV.out" ctdt.c;nmppc QofV.o QofV_data.o rtGetInf.o rtGetNaN.o rt_logging.o rt_look.o rt_look1d.o rt_nonfinite.o nidll_main.o rt_sim.o ode8.o | tclsh c:/gccdist/WindRiver/vxworks-6.3/host/resource/hutils/tcl/munch.tcl -c ppc > ctdt.c abnormal program termination C:\Users\XXX\AppData\Local\Temp\make426012.sh: fork failed: no child processes [1]make: *** [QofV.out] Error 1 ### Real-Time Workshop build procedure for model: 'QofV' aborted due to an error.>>
Solved!
Go to Solution.

Hello jarcTec,
I am not sure right now if you can do it, but this tutorial might help, also everything was made in Winddows 7 in this one.
http://zone.ni.com/devzone/cda/tut/p/id/11654
Take a quick look and let me know if it works!!!
Luis Fernando
National Instruments Cono Sur
Ingeniería de Campo y Consultoría
http://chile.ni.com/

SIT Issues - Undefined Functions and non-compilation

Dear All,
FIrst off hi! Am new to LabVIEW, SIT and the forums. I currently have an issue with SIT 4.0 that I hope you can help me with.
Background:
We are trying to move a Simulink model off of a Windows environment into a cRIO-9004. This will run the simulation on startup and will get its data and will pass its data via UDP links (2 x Transmits, 2 x Receives). The system will not have a host VI, it is to run stand-alone in that respect.
Currently we have a model working fine in Simulink. It communicates both locally and over the network using custom UDP blocks that we wrote in C (and so have src for).
Issues:
Currently when we try to build a DLL from ANY model (even a simple output of a constant) the model will autocode into C and a DLL will build but when importing it into LabVIEW we are told that there are functions defined in the DLL that are not defined in the header (it lists a standard 21 functions [i.e. NISIT_<fn name>] ). The header seems to define a different 4 (or 5 - currently not to hand apologies) <Model name>_<fn name>. These are soemthing like Initialize, Update, Output, Terminate.
So I cannot currently import. The 21 functions seem overkill to manually define in the header but am I wrong? Why is the SIT not writing the header correctly. This issue relates to a model without our UDP blocks, the UDP functionality would be added around the DLL in LabVIEW using standard LabVIEW function blocks.
In addition, rather than directly importing the DLL we considered directly deploying a DLL with the UDP functions embedded in it. However, when using RTW in Simulink it autocodes to C fine, but upon compilation into a DLL is raises issues (in true MATLAB style, typically vague and non-helpful). Any ideas?
Many thanks for any of your time,
Rich
Additional Info:
LabVIEW 8.5 (with Real-Time Module)
MATLAB 2007a
MS VC++ 6.0
The engineer who wrote the custom UDP blocks suggests that it might be an issue with using WinSock in his blocks
Any other info please ask

Adnan,
Thank you for looking into this and I must apologise, my original post wasn't all that clear with hindsight. So I will answer you questions and try to be clearer on the situation:
There are two situations and issues here.
1) Any simlpe model (i.e. constant -> output, or say pulse_gen -> transfer_fn -> output) will happily compile and link to a DLL using you nidll.tlc and the makefile etc that it produces. When importing the DLL (just standard import, not using SIT Connection Manager) I get an error, however:
2) When exporting a DLL (like above) it will load fine onto the target when using SIT Connection Manager, no errors like above. We thought of using this method to do everything in Simulink and use the SIT connection manager as above to load it all. The issue we were having with this is that the UDP blocks that were custom written would not compile when using nidll.tlc and the makefile etc. It will run fine as an s-function in Simulink. The engineer who wrote the blocks thinks it might be that your makefile would not like the UDP blocks as they use Winsock and he assumes that the makefile will raise an error as winsock will not be in the LabVIEW environment.
So to fully answer your questions:
1) What are the exact codes?
When examining the error in Situation 1 that's exactly what I get. Interestingly if I include all the header it lists on the right hand side (clearer in the following screen print) then LabVIEW hangs when adding parsing the "simstruc" headers: (N.B. if you are looking at the addresses of these images then ignore the name of this one!)
The other error I'm getting with regards to the UDP blocks manifests as follows (ignore Paint in the background showing the Config Screen):
2) Does the error occur for any model or just yours?
The errors surrounding the missing functions concerns any model when importing (SIT Connection Manager seems not to mind). The error when compiling/linking the DLL surrounds just our model due to the UDP blocks
3) Are the 21 undefined functions created by you or purely by the Simulink compiler?
We haven't touched any of the files after they are thrown out of the compiler. The 21 or so functions it lists all begin NIRT_<FnName> (N.B. I previously posted wrongly stating NISIT_<FnName>. NIRT_ is correct) so I assume that's the compiler. The ones defined in the header (the 4) all start <ModelName>_<FnName>
The functions I assume I want (copied from the produced header file - I have not edited it. RWFJMildModel is the name of the Model file. There are no instances of the letters NIRT):
/* Model entry point functions */
extern void RWFJMildModel_initialize(boolean_T firstTime);
extern void RWFJMildModel_output(int_T tid);
extern void RWFJMildModel_update(int_T tid);
extern void RWFJMildModel_terminate(void);
The ones LabVIEW finds in the DLL (due to the DLL_EXPORT I imagine) and not the header can be seen in previous screen prints.
4) Are you using nidll.tlc as your System Target File?
Yes all instructions provided online, in the SIT 4 help etc are followed and this includes using nidll.tlc:
5) If the model you are trying to build does not use your custom UDP blocks, then why do you believe the issue is related to using WinSock in those blocks?
The model we plan on using eventually currently includes the UDP blocks, although if we cannot import them we will wrap the UDP functionality around the "rest of the model DLL" in LabVIEW provided we get that working. The other models are simple (as in thrown together in less than 30 secs) and I have no reason to believe this, I think this confusion was caused by my terrible first post, apologies.
Thank you for you help, it is much appreciated
Rich
P.S. My company blocks imagehosting sites so I cannot confirm if the screen prints are in place, in the right order etc. They should however all be there!

Download Older LabView Version?

My campus has a LabView site license, and the easiest way to install LabView without any extra toolkits is simply to download an evaluation and set up a network license for it. We had a computer crash and now need to reinstall LabView, but for the life of me I cannot find an 8.5 download. I do not really want to upgrade to 8.6 at this point (if the campus license even supports it) as that would require updating all our computers to the new version, something I am not really wanting to do at this point. Can anyone direct me to somewhere I can download an 8.5 evaluation copy, or is it 8.6 or bust at this point?
Thanks

Hello,
If you have a site license then you should have the discs to install LabVIEW again, even though to you this may not be as convenient as downloading from the website.
Otherwise, I suggest that you contact NI for support at 866-275-6964 with your serial number in hand. www.ni.com/ask
Have a great day!
Kameralina
Ask NI (ni.com/ask)
Search The KnowledgeBase
NI Developer Zone
Measure It. Fix It. ni.com/greenengineering/
NI Vision ni.com/vision/

SIT unable to 'look under' simulink library link

I have used older versions of SIT. I recently installed LabVIEW 8.2 and SIT 3.0.2. I work with very complex simulink models. As a result all the models I work with have library linked blocks (subsystems) in them. When I tried to use current version (as specified above), I realised that I am unable to browse any deeper than the top level block (which happens to be a library linked subsystem). All I can see in the inputs and the outputs of the block with I got 'mapping' tab of the SIT GUI. My entire model in under this block which consists of various masked subsystems, library linked blocks. I had this problem with a version just before this version (I guess it must be 3.0). I was thinking this would have been addressed in the newer release. Apparently not so. Is this a bug with LabVIEW SIT or a limitation or am I doing anything wrong?
Thanks.
Amit

Sorry Bob, I believe on the second read, my comment also seem to come the wrong way. When I said I have used Matlab/Simulink for over 6 years, I was citing my experience with those tools. I am a fairly new user of LabView/SIT. So, I understand what are the linked subsystem etc. As far as versions are concerned, Matlab version Release 13 SP1 (6.5.1) seemed to have worked fine. This corresponds to Simulink version 5.1. The SIT version 2.0 (or 2.0.2).
I would like to understand what is the cause of the problem. Also, I was able to find a work around, but that is not a workable solution in our case. The reason is most of our model have a lot of library links. The work around is to disable the library link within the simulink model and then establish the connections between the VI instruments and model blocks at all whichever level. Then restore the simulink model library links. It seems to work fine but is not a viable option.

Linux labview eval version for lego mindstorms nxt

Hi,
I'm a high school teacher in Tamil Nadu, India. Our school recently purchased 4 lego mindstorm NXT kits. We were happy to find that the new software was powered by labview, because it runs on linux. Our school runs on an Edubuntu LTSP network. So we were sad when we discovered the installation disk only supported MacOS and Windows.
I looked at the labview site for NXT and saw that we could get a student evaluation copy for use with NXT - so I filled out the forms, but when the link to the FTP site was given, it only provided a Windows and MacOS copy.
Can we obtain a student copy of labview for Linux for use with our NXT kits?
Thank you, Jason Stewart.

Hello Jason,
I'm sorry I didn't make this more clear in my previous post, but the LabVIEW Student Edition for use with LEGO® MINDSTORMS® NXT is only available for Windows. This will provide you with the LabVIEW 7.1 Student Edition and then you can download the LabVIEW Toolkit for LEGO® MINDSTORMS® NXT. This will give you the ability to create custom NXT blocks in LabVIEW.
Another option would be to purchase the latest LabVIEW Student Edition and then download the LabVIEW Toolkit for NXT. However, this edition is also only available for Windows. The customers that are downloading the LabVIEW Toolkit for LEGO® MINDSTORMS® NXT on a Mac OS have purchased the full version of LabVIEW for Mac.
Your best option would be to contact the NI India Sales Office at [email protected] or 91 80-4119 0000. They would be able to help you best with this.
Regards,
Clint M

Looking for german sites

hi!
i am looking for german labview sites?

Check the following information from National Instruments regarding third party vendors. There is a section for Germany.
http://digital.ni.com/alliance.nsf/web/servicebygeography
Regards;
Vargas
www.vartortech.com

Cannot run Simulink dll at the same time as running real-time target VI

Hello
What I am trying to do is run a model dll created in Simulink to control some servo's through a CompactRio 9014.
At the moment I have managed to create three VIs
1) In the FPGA target that performs the PWM on a desired channel
2) That takes the value of a network variable which contains the position required and feeds that to the 1st VI
3) A VI that runs on the host computer that modifies the value of the network variable to change the position
I can get these three VIs working and the servo controlled, but when I try to update the value of the network variable using the simulation, by deploying the simulation to the RT target and running it, it says
'Access denied: This target is already in use by another project or host computer.'
I assume as this is because the project is already connected to the cRio, so I disconnect and am able to deploy the model files.
However when I try to run one of the VIs in the RT Targer along with the simulation I get the error:
'This VI is downloaded on the target but is not present in the project you are attempting to deploy. All VIs on the target will be closed unless you choose to add the missing VI to the project.'
With a large number of missing VIs...
Would I be doing this wrong, i.e. is there a much simplier way to control the FPGA inputs using the simulation, or is there something I could have missed?
Thanks
Geoff
Solved!
Go to Solution.

Hi Geoff,
It seems that you are on the right track except for some concepts that I
want to review:
A CompactRIO or cRIO has 3 different components:
1)
Real-Time controller (in your case a 9014)
2)
FPGA backplane (this could be a 9102, or a 9103, 910x,
etc)
3)
I/O modules (like a 9401, 9263, etc)
When you write an application for cRIO you usually have three different VIs:
1)
Host VI – This VI is used as a user interface and runs in
Windows (under “My Computer” in the LabVIEW project) This VI is optional because
you might want to run the cRIO headless.
2)
RT VI – This is the VI that runs in the cRIO controller
(in your case the 9014). This VI lives
under the cRIO target in your LabVIEW project.
3)
FPGA VI – This is the VI that runs in the cRIO
backplane like a 9102. This lives under
the cRIO >> FPGA target in the LabVIEW project.
The ONE application that I was talking about in my last post is for the RT
VI. There can only be one RT VI that
gets deployed. If you want to run
multiple VIs in the cRIO RT, then you need to run those VIs as subVIs of one
top level VI.
LabVIEW Simulation Interface Toolkit (SIT) has a tool called the SIT
Connection Manager that creates two of these three VIs for you (the RT and the
Host VIs).
Please refer to the following link about the SIT Help. Go to the How To section. It is organized in a kind of step by step
tutorial.
http://zone.ni.com/reference/en-XX/help/371504D-01/
In your case it is going to be a bit more difficult because of two things:
One, you are using a VxWorks target.
Two, you want to use your own FPGA VI.
Let’s address each one of them:
1)
VxWorks target- To use the SIT Connection Manager you
need to use a DLL not an OUT file, even though you need the OUT file for the cRIO VxWorks target. The reason is
that this tool needs to read the compiled model to know what the
parameters, signals, inports and outports of your model are. Because the tool runs in Windows you cannot
open an OUT file (meant for a different OS) so you need to give it a DLL.
For this reason you will need to compile your model file into an OUT
file and a DLL. Once you give a DLL to
the Connection Manager and you select your cRIO as the execution target, keep
doing the rest of the steps as the help says.
LabVIEW will identify that you are using a VxWorks target and will
download the OUT file to the cRIO.
2)
Custom FPGA VI – LabVIEW SIT has some FPGA bitfiles
(compiled FPGA VIs) that it can use.
When you open the SIT connection manager and go to the Hardware IO
mapping section it asks you to select the bitfile. If you want, you can select one of the
shipping bitfiles but iIf you
want to use your own, then you will need to do some changes to your FPGA VI , recompile it and
save the bitfile in a specific location with a specific name.
Please refer to the following link for
instructions on how to create your custom FPGA VI:
http://zone.ni.com/reference/en-XX/help/371504D-01/lvsithowto/sit_h_custfpga/
What I would suggest is that you start with a very simple example and using
one of the shipping bitfiles. Look into
the following path for a very simple Sine wave generation example:
C:\Program Files\National Instruments\LabVIEW 8.6\examples\Simulation
Interface\Sine Wave
Because you are running a VxWorks target you will need to recompile this
example model sinewave.mdl to an OUT file.
To get a better understanding of what SIT does you might
want to check some quick videos. Go to
http://sine.ni.com/nips/cds/view/p/lang/en/nid/11763 and under the
resources tab there are two videos called Demo - <something>...
Hope this helps and let me know if you have more questions.
Ricardo
National InstrumentsSystems Engineering

Help for Seconds to Duration (hh:mm:ss) conversion

I have this SubVI that is to convert Seconds to Duration (hh:mm:ss). This SubVI works fine for converting Seconds below 54000 (15:00:00) but the subsequent Seconds, for instance (57600 seconds), it returns Duration -8:00:00 instead of 16:00:00.
My SubVI is attached below. Would any kind souls please help ??.... thanks...
Note : - I've included the ConvertDurationToSeconds.vi to allow you to convert Duration to Seconds
Attachments:
ConvertSecondsToDuration.vi ‏40 KB
ConvertDurationToSeconds.vi ‏20 KB

Judging by you code and the results you reported I guess you are the other side of the world from me.
I just happened to have worked with a driver that was provided by Cincinati Sub-Zero as part of the LabVIEW driver that supports one of their temperature chambers.
As part of the driver they include a VI that does exactly what you want. CSZ does not support this driver, so do not call them for help. The sub-VI is included below.
The issues that are hitting you here are patially addressed in a memo posted to Info-LabVIEW by Rolf.
I include the same below.
Ben
"LewisDrake" wrote:
>Another annoyance related to time changes is that the LabVIEW XY graphs,
>formatted to show Time & Date on the X axis, generate major tic marks that
>aren't synched to midnight local time. Instead, they place major tics at
>7:00pm (in the US Eastern time zone). Before the time shift, they showed
>major tics at 8:00 pm. Of course, they have always been off by the offset
>between GMT and the computer's location.
LabVIEWs internal time (seconds since January 1, 1904, midnight UTC) are UTC
based. All times displayed on a frontpanel however are in local time which is
dependant on the time zone set in the OS.
>I believe that the major tic locations are determined from midnight GMT
>rather than from midnight local time. To display properly, one must
>configure Windows to use GMT instead of local time and turn off automatic
>time adjustments.
If you want to have a graph set to Time & Data and display only the time to get
a nice 24 hours display for instance (relative time format has unfortunately
not the same formating features as the absolute time) you can easily get that
by setting the X axis offset to the appropriate offset of (24 * 3600 -
(timezone offset)). This is a one time thing when opening the graph window
and then the graph displays fine with 00:00 ......
There are utilities on the Info-LabVIEW site, I believe developed by Stepan
Riha, to get the actual UTC offset correctly calculated. It isn't really
difficult just a little bit diff calculation and proper 24 hours overflow
handling.
>I WISH NI WOULD FIX THIS.
Not so simple without causing many more problems for existing applications.
Also using UTC as internal time format is a good choice, it really is! And
displaying local time for absolute times is also what 99% of the users expect
to see, so a good choice too.
The only workable approach I see is either improve the formating capabilities
of the relative time display to allow similar display formats as in the
absolute time format and/or add an option to the absolute time format to
display UTC instead of local time. But above fix can solve the problem nicely.
Rolf Kalbermatter
CIT Engineering Nederland BV tel: +31 (070) 415 9190
Treubstraat 7H fax: +31 (070) 415 9191
2288 EG Rijswijk http://www.citengineering.com
Netherlands mailto:[email protected]
Ben Rayner
I am currently active on.. MainStream Preppers
Rayner's Ridge is under construction
Attachments:
Time_Conversion.vi ‏49 KB

How to install NI Toolkit Sinks on Matlab R2008a

Hellow
I'm working with LV 2010 and Simulation interface toolkit, but i can't find NI Sinks on my Matlab simulink. Please tell me how to install NI sinks and is there any other way to communicate with .mdl files.
Thanks.
Résolu !
Accéder à la solution.

Bonjour,
Vous postez actuellement sur la communauté francaise. Merci de mettre poser vos questions en Francais.
Pour l'installation de SIT, il faut installer Matkab, puis LabVIEW, puis SIT pour que tous les composants s'installent correctement.
N'hésitez pas également à consulter les fichiers d'aide :
LabVIEW SIT 2010 Help
LabVIEW SIT 2010 ReadMe
Cordialement,
Hello,
You're actually posting on the French Forum, please write your comments in French. If you want to talk in English, please post in the appropriate forum.
Kind Regards,
Olivier L. | Certified LabVIEW Developer

BlockSet for I/O

Hallo All,
bei der test ein TCU habe ich das problem: I/O schnittstellen. Weiss jemand wie kann ich ein Block set für I/O (DI,DO,PWM...) in Simulink defenieren, ich kann jetzt die I/O nur in Labview SIT Connection Manager manuell konfigurieren ,ich will aber in Simulink defenieren ,wie zum beispiel( I/O Blockset von dspace) .
Software:
Labview 8
FPGA Module
Real-Time
SIT
Hardware:
RT NI PXI mit FPGA 7813R
jede Information ist mir sehr Hilfsreich für mein Diplomearbeit.
Danke
Befaiz

Hello All,
I have in the test of TCU the problem: I/O interfaces. someone knows possibility of Simulink and labview around blockSet for I/O in Simulink to define (DI, DO, PWM…), I can configure now the I/O only in Labview SIT Connection manager manually, I want however in Simulink to define, like for example (I/O block set of dspace).
Software: Labview 8, FPGA-Module ,labview Real-Time ,SIT
hardware: RT-NI PXI with FPGA 7813R
Each information is me much auxiliary realm for my diploma work.
Thanks
Befaiz

Comunicacion Labviewy Simulink de Matlab

Buen dia, estoy desarrollando una aplicacion donde tengo comunicarme com simulink de matlab. He revisado varias bibliografias y material....en los cuales me remiten a un servicio SIT Connection Manager, el cual no encuentro en mi version de Labview(2011) y matlab2011a
Muchas gracias
Solved!
Go to Solution.

Hola ivan_1982
El servicio que mencionas, se agrega cuando instalas el Simulation Interface Toolkit para LabVIEW (SIT). Este es un add-on que se agrega sobre LabVIEW y le agrega funcionalidad extra. Dicho toolkit lo puedes revisar y descargar como evalucación, en la siguiente liga:
NI LabVIEW Simulation Interface Toolkit
Sin embargo, para la versión que tienes de Matlab, es necesario descargar la versión de LabVIEW 2012. Esto lo puedes verificar en la siguiente liga:
Simulation Interface Toolkit Version Compatibility
Espero sea de tu utilidad dicha información.
Saludos
Francisco S.
National Instruments
Field Engineer
www.ni.com/soporte

Error with Simulation Toolkit

I have a control DC motor model in Matlab/Simulink. I control Ref value in model through the Labview. I used Labview Simulation Toolkit to do this. I created dll file from simulink model through Realtime Workshop and added it in Labview
( SIT connection manager )
I attacked my files : test1.vi ; test2.vi and test_labview.mdl
My problem is : In test1.vi , I have a knob link to constant box in simulink model and indicator scope link to scope box in simulink model. When I run Labview and change knob value , it acts normally and the respond of simulink model is correct
But when I used test2.vi, I change knob value by changing knob2 value . In this situation , I try to use local variable and value node but It is not succesfull. The respond of simulink is incorrect . The knob value is not link with simulink model. Please help me. I want to change knob value through knob2 value and link to model.
I used Labview 8.6 and Labview Simulation Toolkit 5.0
Attachments:
test 1.vi ‏67 KB
test 2.vi ‏68 KB
test_labview.zip ‏7 KB

First of all the SIT was not really meant to be used with HW on Windows because it is not deterministic. That being said, it could be a slight hassle to add hardware support to the SIT client VI.
The value change event does only get fired if the user changes the value on the UI by clicking the increment/decrement button and/or by typing a new value or if the property 'VALUE (Signaling)' is used. Since the source of the value update in your case is not a user input but the input value of a DAQ board, you have to use the ladder mentioned option.
Message Edited by ThSa on 04-05-2010 11:17 AM
http://www.newgistics.com
Attachments:
Image1.png ‏15 KB

This is regarding counting with microsecond accuracy and furthur simultaneous AO and counter usage

hi, i am in seruios trouble. I am doing photon counting using a PMT. so the TTL pulses come at random and the i canhave 1e6pulses/sec tp 1pulse per sec kind of TTL pulses. I need to count them with an accuracy of [ time bins ] 50 microseconds. I am not able to do this with all the possible examples i have seen on labview site as well as that which come with labview package. everything shows some or other error. I have been using labview for analog I/O for about 2 years and have done the most i could understnad but to of no use. does anyone have a sample program ? now the bogger problem is that while counting these TTL pulses i ALSO have to do an analog output [ say a triang
ular wave on AO channel ]. I was wondering that if i just add the AO vi's in the counting programme will they interfere with each other ? [ I have a very crude counting program which atleast gives me millisec accuracy limited by for-while loops ]or i shd trigger start them together [ counting and AO] and some how make sure that they do not interfere with eacht other. If anyone could help me with either or both program..i'll be very grateful.
gvs

A simple event counting example can count TTL pulses for you pretty easily. If you have an E-Series board, the DAQ-STC counter/timer uses a 20 MHz timebase, so your pulses must be separated by at least 50 nanoseconds. The 660x family of counter/timer boards use an 80 MHz timebase giving you a tighter window of 12.5 nanoseconds.
For your second problem, it's best to use dataflow and enforce a well-defined execution sequence. In other words, wire the error clusters such that AO always executes after (or before) your counter operation.
In fact, you must enforce serial execution of DAQ VIs to avoid blocking if you are using Traditional NI-DAQ. If you are using the new DAQmx, DAQ operations are supposedly non-blocking in many scenarios. I have not tried to ve
rify that for myself so be cautious if you plan to run AO and counter code in parallel.

Simulation Interface Toolbox: Problems using sbRIO with Tutorial: "Using the Example Sinewave Model with a VxWorks CompactRIO Target"

Hello
I faced a problem when I tried to do the Tutorial "Using the Example Sinewave Model with a VxWorks CompactRIO Target".
My specifications are:
Software:
Win7 64-bit
Matlab 2010b with RTW (to compile the *.dll) (32-bit)
GNU-Toolchain 6.3 running in Virtual PC-XP-Mode (to generate the *.out)
Labview 2011 with Simulation Interface Toolbox 2011 (32-bit)
Hardware:
sbRIO-9631 (from Labview Embedded Platform Evaluation Kit)
I was able to compile a dll and an out file.
I created a custom fpga-Bitfile with the Tutorial "Creating a Custom FPGA Bitfile".
In a blank VI I made the Host-VI and with the SIT Connection Manager I created the Driver VIs.
Until here everything worked fine.
Now my problem appeared. As long as I don't create Hardware I/O Mappings my model runs fine on the sbRIO:
But when I try to map the in and out port of the model to a HW I/O I get this error:
What causes this error?
On my sbRIO following software is installed (followed this instruction: Configuring a Real-Time Target to Run the LabVIEW SIT Server)
Best regards
Patrick

I have exctly the same issue. here is my error
my fpga for the bitfile
my driverVI
and my installed software

LabView SIT

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