LabVIEW / DAQ / FPGA / Vision 基本練習題

附件是 LabVIEW / DAQ / FPGA / Vision 實機操作的習題，歡迎大家下載多多練習!
LabVIEW 習題
DAQ 習題
FPGA & CompactRIO 習題
Vision 習題

Hi Gary,
My suggestion is to first work from the Vision RIO examples in the example finder. All of the examples are commented and should at least help you get started. Also, check out this tutorial on Digital Camera Basics, you will notice many of the concepts talked about here in the code itself.
http://www.ni.com/white-paper/3287/en
You are correct in your assumption that the image comes in pixel by pixel and you can read more about the image's construction in the article and see that construction in the example codes.
Cole R.
National Instruments
Applications Engineer

Similar Messages

Ask for help with LabView Daq and Tek VX4244 VX4101

I use NI VIO-MXI-64XE-10, Tek VX4101 and Tek VX4244 to acquire data in one
Tek 1410A VXI mainframe connected a PII 350/64M computer with MXI2
cable.these modules are used for three independent applications,the datum
are acquired and through preliminary computation, then sent to three TCP/IP
ports the computer served in real time. the burden of the system will be
very heavy because the 64XE-10 need to use up the 100K sample rate
continuously dealed by 50 channels,and the VX4244 need about 30Hz for all 16
channels.
64XE-10 is easily detected by NI software, and I can use LabView Daq
intermediate analog input VIs to acquire data in background, read 50 samples
and compute the mean for each channel,then packa
ge the 50 mean and send to
client end with 40 times a second. I found the speed is satisfactory.
As for VX4244 and VX4101,I can't use LabView Daq VIs,and the driving
functions for LabView with the product are difficult to understand, I want
to know how I can get data and send out efficiently,how to get data in
background,and how to use FDC ?
And for 64XE-10, although the speed is satisfactory, but it use much more
CPU resource, I want to use advanced analog input VIs to build the code,I
want to know where I can find examples using the advanced analog input VIs ?
Best Regards

I use NI VIO-MXI-64XE-10, Tek VX4101 and Tek VX4244 to acquire data in one
Tek 1410A VXI mainframe connected a PII 350/64M computer with MXI2
cable.these modules are used for three independent applications,the datum
are acquired and through preliminary computation, then sent to three TCP/IP
ports the computer served in real time. the burden of the system will be
very heavy because the 64XE-10 need to use up the 100K sample rate
continuously dealed by 50 channels,and the VX4244 need about 30Hz for all 16
channels.
64XE-10 is easily detected by NI software, and I can use LabView Daq
intermediate analog input VIs to acquire data in background, read 50 samples
and compute the mean for each channel,then packa
ge the 50 mean and send to
client end with 40 times a second. I found the speed is satisfactory.
As for VX4244 and VX4101,I can't use LabView Daq VIs,and the driving
functions for LabView with the product are difficult to understand, I want
to know how I can get data and send out efficiently,how to get data in
background,and how to use FDC ?
And for 64XE-10, although the speed is satisfactory, but it use much more
CPU resource, I want to use advanced analog input VIs to build the code,I
want to know where I can find examples using the advanced analog input VIs ?
Best Regards

Where can I find LabVIEW 2012 FPGA module

Hi
I uase LabVIEW 2012. Could you please let me know where can I find LabVIEW 2012 FPGA module to download?

Where are you entering your serial number? I am able to simply download it using the webpage:
EDIT:
You could also try downloading it with direct links:
1. NI Downloader for FPGA Module 2012: http://download.ni.com/evaluation/labview/ekit/other/downloader/2012FPGA-Eng_downloader.exe
2. Installer for FPGA Module 2012: http://download.ni.com/evaluation/labview/ekit/other/downloader/2012FPGA-Eng.exe
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
If someone helped you out, please select their post as the solution and/or give them Kudos!

Is there possible to save LabVIEW 2009 +FPGA 2009 source as 8.6 version.?

Hi,
I am using Labview 2009+FPGA 2009 development software. But my customer only have the Lv8.6's license. so i hope to know does the source code of LabVIEW 2009 +FPGA 2009 can be saved as 8.6 version? As I know, the labview of 2009 code can be saved to the earlier version. But i am not sure if the FPGA code work or not.

Hi ivan,
just try!?
Best regards,
GerdW
CLAD, using 2009SP1 + LV2011SP1 + LV2014SP1 on WinXP+Win7+cRIO
Kudos are welcome

PCI-6251 into LABVIEW DAQ Assist block interruptions and resets

Signals being received from PCI-6251 into a LABVIEW DAQ Assist block interrupts and resets every 10 seconds after 1 minute of data acquisition. Would this be a memory buffer problem or is it something related to the hardware? I am using a BNC-2110 hardware connector. Please view the attached image.
Attachments:
Interuption1a.GIF ‏4 KB

Hey Peter,
Ahh, I understand the graph now! Hmm, this is very strange behavior. Instead of using the DAQ Assistant, try to use the explicit DAQmx VIs (see picture). You have more explicit control over what is going on with the DAQmx VIs and keep as much as you can out of the loop.
Regards,
Erik
Attachments:
analoginput.JPG ‏23 KB

LabVIEW 2010 FPGA Driver for Xilinx SPARTAN 3E Starter Board

Dear Friends,
Is there any possibility to release a LabVIEW 2010 FPGA Driver for Xilinx SPARTAN 3E Starter Board?
Regards,
wedo
Solved!
Go to Solution.

Hi Brad,
So glad to get your post here!
I’m looking forward to download the new installer.
I wonder whether the new driver will support the 10/100 Ethernet Physical Layer Interface, since the last drivers aren’t support this feature!?
Also, will be any new examples included with the new driver? For instance: an example for the StartaFlash Memory; I have done an example for this but I couldn’t get it work! I don’t know why! You may check my post and the example in the following link!
http://forums.ni.com/t5/LabVIEW/Spartan-3E-StrataFlash-Memory-wrong-reading/m-p/1030898
By the way, is there any plane to develop a driver for the Spartan-3E (1600Kgate) kit? Both kits (500KGate and 1600KGate) have the sample on-board peripherals, the only difference is in the number of Gates (FPGA chip). I think all that is needed is to add the component ID (29597843---->3E1600) and revise the xc3s1600e.bsd and 3sXXXe.nph.
Thanks in advance & kindest regards,
wedo

2.7 year experiance in labview, DAQ, PXI, PCI seeking job

chennai based
2.7 year experiance in labview, DAQ, PXI, PCI seeking job
Attachments:
sen 3.doc ‏81 KB

Thanks for your help,
I've finally got rid of the errors, but when i run the VI while using the potentiometer, i'm not getting any readings on the graphs (on the front panel). I've checked for errors but cannot find any...
Any help is appreciated,
Thanks
p.s. i've attached the VI so you can see what i mean...
Attachments:
Pitch Analysis1.vi ‏321 KB

LabView DAQ running more stable under Linux?

Hello,
We are doing LabView DAQ using a cDAQ9714 module (with AI card 9203 and AO card 9265) at a customer site. We are running an excutable on a Windows PC and had a couples of times (3 so far) that the PC just gone freeze for some reason and we lost all inputs and outputs. Each time it happend after the program continous run a few days. So far we have no clue why this is happening (Any idea?)
We need the program to run continously for months and years and absolutely hate the fact that it freeze. Since we couldn't find any bug in the program till now, we're thinking to blame Windows. Then alternative for us is to use Linux os. My questions are:
1. Does LabView run stable on Linux than on Windows? Any data or experience anyone has?
2. To get the same program runs on Linux, I heard I have to buy a LabView Linux delelopment tool and create the excutable from there. Does this involve any extra effort than the Windows one?
3. Does NI have any industrial PC that has Linux OS preinstalled instead of Windows? We bought one PPC 2115 before.
Thanks!
Rgds,
Harry

Harry - the main link here: http://zone.ni.com/devzone/cda/tut/p/id/6909 will show DAQmx (some Linux) and DAQmx Base (Linux/Mac) support for all of our products. It's the same table on the last link it just links a list for all of our hardware offerings. Currently there aren't any offerings with your desired I/O, we have a few multifunction DAQ devices like the USB-6218 that can be programmed with DAQmx Base in Linux. If you are looking to run stand-alone and highly stable applications you may want to look into programming an application with the LabVIEW Real-Time Module and deploy it to a RTOS (Real Time Operating System) controller. You would program the application in Windows with LabVIEW and this additional module, and then distribute the program to a controller. If you deployed to an industrial controller you can interface PCIe, USB buses etc for your DAQ instruments. We also offer this in our CompactRIO form factor where you would deploy the application to a controller/C series chassis similar to the compactDAQ you are using now in that it houses those C series modules but has much more to offer. I've put a few links below here if you would like to look into these products any further.
NI 3110: http://sine.ni.com/nips/cds/view/p/lang/en/nid/206847
NI CompactRIO: http://www.ni.com/compactrio/
NI 9074 Integrated 8 Slot Controller-Chassis: http://sine.ni.com/nips/cds/view/p/lang/en/nid/203964
Regards,
Ben N.
Applications Engineering
ni.com/support

Help Labview 2012 FPGA module

Hi
I have a project on Spartan 3e with Labview program but I can not install the driver cause of labview 2012 FPGA module
Thanks

Hi again
Why i can't download the fpga module on this link : http://www.ni.com/download/labview-fpga-module-2012/3088/en/
can anyone send me a link to download the module?
Thanks

Incorrect AMUX/PCI6025 readings using Labview/DAQ

I have an AMUX64/PCI6025. Using my DVM, I measure the voltage at the AMUX screw terminals on various channels with correct readings obtained. Performing measurements with Labview/DAQ are incorrect. What is causing this?

Hello;
The first thing to double check is if the input mode is set accordainly with the connections made.
The best bet is to revisit the AMUX Users Manual and double check the connections you made with the ones shown in the manual. Furthermore, go to MAX and check the input mode of the DAQ device.
Everything must match.
In case you got everything accordainly with the manual, and you still see the same behavior, the problem is probably hardware related.
Hope this helps.
Filipe A.
Applications Engineer
National Instruments

DC to DC converter basics using Labview on FPGA Control with VHDL

DC to DC converter basics using Labview
I am fairly a novice, that is why simplifications required, before I begin thanks in advancefor them who will response
I am designing a DC to DC (Intermediate Bus Converter, a step down BUCK converter, of 24 v input and output 9 v and 5 amp current output), using FPGA controller, I need to program this using VHDL, for which I take LabVIEW, but as I am new so do not have any idea as what are the steps that I need to take for implementation, what types of function that FPGA does in this so that it can generate 24 v and what other mechanisms that have to control inside or outside of FPGA programming and designing that it can give the desired output voltage, if you have any idea about this then I would be glad to receive the steps that are necessary to complete this

NI supports two Spartan 3E products through either LabVIEW FPGA or MultiSIM, the Digital Electronics FPGA Board (http://sine.ni.com/nips/cds/view/p/lang/en/nid/207010) and, if you are in academia, the Xilinx Spartan 3E XUP starter board (as linked by Dennis_Knutson).
Also note that if you wanted to implement some logic in VHDL and have access to that logic in a LVFPGA diagram, you could utilize the Component-level IP (CLIP) fuctionality (http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/using_component_ip/)

Labview 2011 FPGA Compile Error

Hi,
I'm new to FPGA. I want to use Labview 2011 SP1 with the Spartan 3E starter kit from Xilinx (Spartan 3E driver available from NI labview website).
I'm trying to work my way through the examples that came with the driver. I've run into the same compiler error with a number of the examples. The error is attached.
Error 7 occurred at Read from Text File in niFpgaCompileWorker_CheckForErrors.vi->niFpgaCompileWorker_JobComplete.vi->niFpgaCompile_Worker.vi:1
Possible reason(s):
LabVIEW: File not found. The file might have been moved or deleted, or the file path might be incorrectly formatted for the operating system. For example, use \ as path separators on Windows, : on Mac OS X, and / on Linux. Verify that the path is correct using the command prompt or file explorer.
C:\NIFPGA\compilation\Shift_FPGATarget_Shift_87E8371C\Spartan3EStarter.bld
I've checked the registry to ensure that the path to the compiler is correct.
Any assistance would be welcome.
Regards,
James.
Attachments:
Labview2011_FPGA_CompileError.JPG ‏96 KB

Hi,
I don't have any Xilinx tools installed - other than the ones that installed with the Labview FPGA module.
I have attached the compilation logs and output results from my attempt.
I have renamed the extension on the following files from .lvtxt to .txt
BuildResults.txt
CodeGenerationResults.txt
Regards,
James
Attachments:
BuildResults.txt ‏5 KB
XilinxLog.txt ‏42 KB

Can Labview DAQ work on a self-triggering basis?

Currently I have the following setup:
We shoot electrons through a diamond (which is attached to a electronics board via electrodes), then the electrons pass through a scintillator. We use the scintillator/phototube as the trigger pulse right now, but I want to be able to instead trigger on the diamond itself. Is it possible to self trigger?
Any suggestions?
Thanks

If the board connected to the diamond outputs a pulse and the pulse is what you want to measure then sure, you could wire it to both the analog input and also your trigger channel. You can set up various trigger conditions. If the pulse is TTL (or close), you use digital triggering. If it's an analog signal, you can set the threshold and other parameters to control triggering.
There are many ways to control DAQ triggering. Have you checked out the examples that ship with labview? Open the Example Finder (Help>Find Examples...) and search for 'trigger'. That should give you some ideas to get started.
Using LabVIEW: 7.1.1, 8.5.1 & 2013

CPU accessible registers in LabView FlexRIO FPGA

Howdy folks, I am wondering if it's possible to get the following behaviors out of Labview. I'm thinking it's not.
System description: CVI application that communicates with PXIe FlexRIO via controls and indicators.
Problem: Designing to a CPU-FPGA interface specification which lists "registers" as a combination of read and read/write bit-fields.
Example:
According to the spec, there should be a 32-bit register. Bits 31:16 are read-only, and bits 15:0 are read/write, from the perspective of the CPU. In the labview world, I would just make a uint16 control, and a uint16 indicator and be done with it.
However, to meet the spec (written for traditional microprocessor buses), a 32-bit read to an address should read back the full contents of the 32-bitregister at that location (implemented as flops on the FPGA, with appropriate memory mapping within the FPGA device). Similarly a 32-bit write to an address should store values to that register (appropriately masking writes to bits 31:16 within the FPGA device).
Is there a way for me to have a single address (basically, a single labview block diagram component) that will let me accomplish this behavior? It looks to me like the only solution is to pack my registers with bit fields that are all read, or all read/write in order to fit in with the labview paradigm. That means the spec will have to go back and be re-written and re-approved.
Thanks in advance,
-J
Solved!
Go to Solution.

Nathand,
Here is the standard paradigm (some simplification):
1) C helper file that contains #defines that describe the memory map. things like BASE_ADDRESS, DEV1_OFFSET, DEV2_OFFSET, REGISTER_1_OFFSET. To get to a
2) C procedure which calls things like void setRegister(uint32 *memory, int device_offset, int register, uint32 new_data, uint32 write_mask). and uint32 getRegister(int base_address, int device_offset, int register).
3) If I want to write the value 0xABCD the upper 16 bits of a 32-bit register (register 5), to device #1, I would code:
main(){
setRegister( ptrMemory, 1, 5, 0xABCD0000, 0x11110000)
This would compute the PCIe address based on some equation like BASE_ADDRESS + DEV1_OFFSET+register_offset<<2 (byte addressed).
Suppose this gives us a 32-bit address of 0xC000_4000. We would issue a write across PCIe to address 0xC000_4000. The memory map in the FPGA is programmed such that a set of flops will latch the data in the PCIe write when write_enable = 1, and address 0xC000_4000 are both true. That completes the register write to the FPGA.
A similar thing occurs for a register read. In this case however, when read_enable = 1 and address = 0xC000_4000, the values held in that same set of flip flops is now written onto the PCIe as a transaction. The software application recieves the value and returns that value from the getRegister function.
In my example above, you notice that the same address on the PCIe is used for reading and writing. I am trying to understand if I can have software read AND write from the same address.
When you compile an FPGA, labview creates a (seemingly) arbitrary address translation for all CPU accessible structures, meaning FIFOs, controls and indicators. It assigns different addresses for every single item, and it may or may not keep the same address depending on whether any modifications were done to controls/indicators/fifos since last compile.
I am trying to understand how labview works, so that I can assess whether or not I can read/write from the same address. This matters, because if I can pack bit fields into registers more efficiently in the FPGA, that reduces the amount of functional tests to write and execute to verify the FPGA functionality.
So, a restatement of my original question: is there some mechanism with using controls indicators where both the FPGA AND the CPU can write to the same set of flipflops in the FPGA? If I use an indicator, the FPGA can write to the indicator but the CPU cannot. If I use a control, the CPU can write to the control, but the FPGA cannot. Is this correct?
-J

Newbie Question -- Simultaneous Execution for Labview/DAQ

Hey, I am an undergrad student who is fairly new to labview and control systems and I am working on a senior project. I am wanting to use labview to simultaneously control two separate machines. Both machines would send back data to be saved to a file. They would both be connected to a NI DAQ(SC-2345). Is this reasonably attainable? Will labview and/or the DAQ have problems running two machines simultaneously? I would love any suggestions. Thanks

Let me see if I have your setup pictured correctly. You have 1 PC, 1 DAQ card that is connected to the SC-2345 signal conditioning carrier. Do those modules, you have two different physical machines you want to control. Am I correct?
Do you want to have one LabVIEW application controlling both machines independently? Or two different LabVIEW applications each controlling one machine?
Your one constraint is that since there is only one DAQ card, all DAQ functions have to be handled at a single point of code otherwise you'll get errors about resource conflicts. In other words, you can't have two separate programs eaching trying to work with a single DAQ card.
So you can have a single point of interface with the DAQ card and use architectures such as Producer/Consumer to pass messages back and forth from your other parts of the code. The other parts of the code can be two independent loops that handle the machine control logic for each machine.
The easiest to program would be to have on application that handles both machines. It would have 3 loops, two loops where each loop is for logic for each machine, and one loop that handles the DAQ communication.
If you want to have two separate applications, you can do that as well where each application handles the machine logic and a third background application handles the DAQ communication. It just needs a little bit more sophisticated communication scheme to pass data between the different applications.

LabVIEW / DAQ / FPGA / Vision 基本練習題

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