Maximum SPI clock frequency

Question

Hi, I have a question about the myRIO 1900 spec.
The onboard FPGA has a 40 MHz clock, thus as described here it is possible to generate a 20 MHz frequency. That page also provides an equation for valid frequencies:
The following equation calculates frequencies that you can generate for serial peripheral interface (SPI) I/O on the NI myRIO.
fSPI = fclk / (2 * N * [X + 1]) 
where fSPI is the desired SPI frequency
 fclk is the base clock frequency
 N is the clock divisor
 X is the number of counts before changing the signal
The PWM Express VI and SPI Express VI provide a Validate button that you can use to validate whether the Express VI can generate the frequency that you specify. If the specified frequency is not valid, both Express VIs coerce the specified value to the nearest valid value.
However, the VI limits the frequency to 4 MHz, and 4 MHz is the maximum SPI frequency stated in the user guide / spec. So the question is, why the inconsistency? Is it possible to use the FPGA to run SPI at a higher frequency, such as 10 or 20 MHz? Or is there some unmentioned constraint on N or X in the above equation?

Answer 1

Hi Lack,
After researching this issue, it turns out that all of the default functions VIs, including the advanced VIs for myRIO, will coerce the SPI maximum frequency to 4 MHz because this is the highest range that NI officially supports. Technically you could try for higher frequencies by changing the fixed myRIO FPGA personality and accessing the registers available there, but we cannot guarantee its accuracy.
David H.
National Instruments