MIMO vs 10 MHz Reference

I am attempting to recreate the scenario detailed in the this whitepaper from the Ettus site....
http://www.ettus.com/content/files/kb/mimo_and_sync_with_usrp_updated.pdf
...which uses an external RF source, with a carrier at a small IF relative to the USRP. The white paper shows that by using the MIMO cable...the measurements between two USRPs can be phase locked and synchronized. I recreated this with two N210's with WBX's and the LV driver....EXCEPT...instead of the MIMO cable...I used only a common 10 MHz reference.
Upon initiating and fetching packets...I note that within a fetch...the data appears phase and frequency locked, with some constant phase offset. However, if running continuously...with each new fetch that is displayed...the relative phase between radios appears to change (yet is still constant over that fetch).
My understanding is that the MIMO cable provides not only the 10 MHz reference...but also timing information such that "t0" is the same between radios. Using only the 10 MHz reference...I understand that can't be assured that the data between radios was in fact taken at the same time. I anticipated that this "synch offset" would change every time I configured the radio....but should at least be constant when observing multiple fetches over time after a single configuration event.
This is not what I see. It's as if the constant phase offset changes fetch to fetch.
Any idea what's going on here? What's different when I use the MIMO cable vs the 10 MHz reference only?
Brandon
However...I expected this to result in some kind of phase offset which would remain *constant* between fetches (nothing is changing between fetches).

Initially, no. My understanding was that using the 10 MHz would have phase locked the two, but the samples wouldn't be synchronous because I wasn't latching in a time via the PPS. This should have just resulted in some initial phase offset, which would have been fine for my application. However...it appeared that instead of a constant phase offset between the two radios...I was seeing a slightly varying phase offset between fetches.
The code I initially used had two parallel processes to configure/initiate/fetch from two radios. However...since then...we've combined the configure/initiate/fetch into a single process using the ";" separator and fetching data using the "complex array" polymorphic Fetch VI. This approach does not appear to have phase 'jumps' between fetches...and results in a constant phase over time. Not sure yet why the two approaches would have caused what I've seen....but the second approach seems to do the trick.
Still...it would be good just to get a second opinion that by using only the 10 MHz reference and not the PPS that my measurements would still be phase locked...just with some constant phase offset because I'm not synchronous.

Similar Messages

5600 Downconverter : 10 MHz Reference CLOCK

Hi RFSA Guys,
Is it possible to vary the 10 MHz Reference Clock and use it ... for demodulation of RF Signals
to a new value ... lets say 9.9992 MHz ?
If this is possible, upto what resolution can I vary the clock..
Can I vary it terms of 0.1 Hz or 0.01 Hz.. Is the 10 MHz Reference Clock truly that stable ?
I have a competitor clock which is stable upto 0.01 Hz... but not in PXI Form.
If this is not possible, Can anyone suggest a PXI Version of a Variable Stable External Reference Clock ?
Basically, I am looking at varying the Reference Clock to vary my Symbol rate for a Device Under Test.
Thanks for your help..
Dharmendra

Dharmendra,
You might also run into problems when the downconverter tries to phase-lock to that reference clock, since it's expecting 10 MHz. Can you tell us a bit more about what you're trying to do? There might be a different way to accomplish it. Thanks!
Chad B. » National Instruments » ni.com

How to get 10 MHz reference clock out of PCI-5922

Hi,
I am evaluating PCI-5922 for the my application.
In my application, PCI-5922 will get signal from agilent 33250 function generator and both instruments will be triggered at the same time with the same trigger signal.
Is there any way to take out reference clock (10 MHz) out of PCI-5922? If that is possible, synchronizing can be easier.
I am expecting to have answers from experts!
Zeehoon
Solved!
Go to Solution.

Hi Zeehoon,
There are two steps to export the 10MHz reference clock out of the PCI-5922.
1)Specify the reference clock source (to use the internal reference select "no source")
2)Specify the reference clock output (a list of valid terminals can be found in the PCI-5922 Routing Matrix inside the High Speed Digitizers Help)
Here is a LabVIEW snippet showing the clock exported to PFI 1:
-Jennifer O.
Message Edited by Jennifer O on 09-16-2009 04:00 PM
Attachments:
ExportReference.JPG ‏11 KB

Phase difference of GPSDO 10 MHz signal

Hi everyone,
I am comparing the pahse difference of two GPSDO 10 MHz signals on an oscilloscope.
I think that if the GPSDOs are locked onto GPS signal, the pahse difference is very small and almostly stationary.
But, when I measured, the phase difference was chaning from -107 to 260 constantly.
I am sure that they are locked onto GPS, because I have seen the message "GPS is locked" by "query_gpsdo_sensors" command.
What is wrong?

Hello!
Can you describe what you are attaching to the oscilloscope? The output of the GPSDO is a 10 MHz waveform. This should be aligned between the GPSDO's. The derrived local oscillators from the two devices will not be phase algined.
Phase Alignment vs. Phase Coherence
Sharing the common 10-MHz reference among USRPs allows a phase-coherent Local Oscillator (LO) to be synthesized using a fractional-N frequency approach. During synthesis, as the reference is divided, the phase may lock on either rising or falling edges producing a constant but arbitrary phase offset on each channel. In MIMO communications, these fixed yet arbitrary phase offsets are corrected by the same algorithms that perform multipath estimation and correction.
Beam forming applications however require phase alignment of the LO, so that phase can be controlled or captured through baseband I and Q. Clever methods have been used to detect the phase offset in the USRP using a know reference signal and then apply the correction to the received signals for receive direction finding and beam forming research.

External reference for USB 5132

Hello,
I have a couple (hopefully) general questions about using an external reference clock on our USB 5132 digitizer. We want to lock it to the other oscillators in our system, all of which are presently locked to one 10 MHz reference. If I connect our existing 10 MHz reference to the PFI1 input, my questions are:
1. Is the 5132 now locked to our system? Or, do we need to specifiy in the setup software that we want to override the 5132's internal reference and rely entirely our external reference?
2. In order to have the best possible lock, do we need to tell the 5132 to sample at a frequency that is evenly divisible by 10 MHz (e.g. 20 MHz, 10 MHz, 5 MHz, 2 MHz, etc.)? Similarly, are we worse off if we want to sample at say, 13 MHz?
Thanks for any thoughts.
Best regards,
Penny
Solved!
Go to Solution.

Hello Penny,
1. Yes the 5132 is locked to your reference system 10MHz clock (with some offset due to delay in the time it takes to transmit the clock signal from your system to this USB device) if you selected the PFI line as the source of an external timebase. Please take a look at the following example Help>>Find Examples>>Hardware Input and Output>> Modular Instruments>>NI-Scope>>Features>> niScope EX External Clocking.vi.
2. No, although I would expect that if you enter in 13MHz and your device was not capable of doing this it would coerce it to the closest value. I would suspect that only integer divide downs from the clock in question are valid such that 12. 5MHz is the value it would coerce to if you were to request a 13MHz value (with a 50MHzexternal clock). The 5132 can not do RIS so sampling at 20MHz with a 10MHz SampleClock Timebase Source is not feasable.
Regards,
Izzy O.
Applications Engineer
National Instruments
www.ni.com/support

Can we lock 80 MHz timebase to PXI_CLK10 on PXI-6220 M Series DAQ?

I am using PXI-6220 to measure Frequency/Period of 32768 Hz clock signal, accuracy is very important. I have provided signal to measure on Gate input of Ctr 0 (PFI 9). I am using 80 Mhz Timebase. I want to Lock PLL to PXI back plane 10 MHz reference (PXI_CLK10) which in turn is locked onto the 10 MHz reference via PXI-5600 on Slot 2 (External 10 Mhz standard is connected). so far I don't see a way to lock PLL to PXI_CLK10. Is that possible at all? see the image attached to this message.
Attachments:
M Series DAQ Question.png ‏62 KB

Hello Abhatti,
Based on the diagram that you have attached, the M-Series card can PLL to a higher accuracy clock such as the PXI Clock_10. The way to configure this change using the DAQmx driver is route the signals using the DAQmx Timing RefClk.Src Timing property node. Once you place down this property node, and specify the RefClk.Src attribute, you select the PXI-Clk10 as your reference clock source. This will discipline the 80 MHz Timebase of the DAQ card to the 10 MHz reference clock of the PXI chassis. Which chassis are you using? Also, how have you PLL'ed the 10 MHz backplane clock to the PXI-5600 Downconverter?
Michael L.
Applications Engineer
National Instruments

Synchronization of three USRP-2932

hy everyone,
I am using three usrp-2932 to build a system of three synchronized Receivers
Referring to the example of 8x8 MIMO system, it use one gigabit ethernet interface and through switch to connect the eight USRP
But, in my application, i use 12.5MHz as my sampling rate. Besides, due to the concern of the throughput, i use three individual gigabit ethernet interface to connect the 3 usrps.
So, I am wondering that using 3 gigabit ethernet interface will influence the Synchronization of three USRP-2932 or not?
Because it is hard to confirm that the 3 gigabit ethernet interface will send the message to the 3 usrp at same time.
Besides, i was using MIMO cabel to do Synchronization of two USRP-2932.
And now i am using GPSDO to do Synchronization of three USRP-2932.
But, in my experiments, it seems that the performance of Synchronization via MIMO cable is better than using the GPSDO.
So, i am wondering that is there any better way to setup the system. Using external clock and PPS ?

Synchronization options with best performance listed first:
---- Very Best
0. NI FlexRIO SDR and VST offer sharing of local oscillator among devices giving both time, frequency, and phase alignment among multiple channels. (cabling them together is required.)
----- Best USRP Sync Options
1. MIMO cable (2 devices). It synchronizes off of the 10 MHz reference and shares the time base over the link.
2. Clock Distribution (>2 devices) best is using an octoclock or other clock distrubiton method: https://www.ettus.com/product/details/OctoClock-G
(Using the 2932 you will have to power down the internal GPSDO to use this method, as well as move a jumper because it shares the same line as the external SMA inputs.)
------- Better USRP Sync Options
3. GPS Disciplined Clock with GPS Lock (>2 devices) can provide you up to 50ns of synchronization. For best performance all devices need to be able to lock to the same satellite constellation and be stationary.
------- Good USRP Sync Options
4. GPS Disciplined clock with NO GPS Lock (>2 devices) gives you better frequency accuract but does not synchrnoize between devices.
5. Standard USRP with internal TCXO (>2 devices) is equivalent to no synchronization and you will need to consider frequency offsets between devices.

Phase Lock problem with a PXI-1000 chassis

As already discussed here, we had an application running smoothly on a 1042 chassis with a 8186 controller.
We generate two sine waves in phase quadrature, using two 5411 boards.
Unfortunately, we are now obliged to use a PXI-1000 with a 8170 controller, and we don't get anymore the expected results : the signals are generated with the correct frequency and amplitude, but the phase offset is totally unstable, as observed on an oscilloscop.
We are using the Synchronized wave generation NI example. Are we missing something ?
Please consider that we are not specialists in electronics, just plain biologists .
We need help URGENTLY !!!
Chilly Charly (aka CC)
E-List Master - Kudos glutton - Press the yellow button on the left...

One thing that I noticed between the 1000 and the 1042 is that the 1000 has the Fan integrated with the power supply, so the fan is probably run off AC. In the 1042, the fan is run off DC and as stated in the specifications greatly reducing electronic noise. It could be that your phase offset is caused by the AC fan in the 1000.
You might want to try to move everything as far away from the power supply and fan as possible (if it is possible) to see if this helps at all.
Also, the 1042 and 1000 have a 10 MHz reference signal for timing pusposes to each of the modules. The 1042 has an accuracy (skew) of 250 ps between each of the mudules. The 1000 has a skew of 1 ns, obviously much greater of an error (less accurate), which could be causing some issues as well.
I do not know what freq you are operating at, but you may be able to filter some of the 60 Hz frequencies out with a smaller capacitor 0.1uF or so.
Good luck.
Kenny
Kenny

5450 Test Panel error

Hello,
I am trying to execute a vi using PXIe 1065 with NI 5673 RFSG and NI 5663 RFSA. When I try to test NI 5450, using MAX, it passes self test but upon clicking the Test Panel and running it using start, the sine wave isn't running and I donot get an amber light on the device's LED? Also after some time i get the timeout error!
Please help.
Regards,
prads

Hi Prads,
First, make sure you have configured the PXIe-5611 Properties page, setting the PXI-5652 as the LO source and the PXIe-5450 as the baseband arb.
Next, make sure there is a cable running from the PXI-5652 REF IN/OUT to the PXIe-5450 CLK IN, assuming you are not trying to lock the PXIe-5673 to an external 10 MHz reference.
Also try running self teston each of the three individual modules, and try Test Panels on the PXI-5652 and PXIe-5450 individually to see what happens.
Let us know what you find. Also, if you can post a screenshot of the error if you are still receiving one that would help.
Thanks,
Andy Hinde, MBA
Systems Engineering - RF
National Instruments

How do I get started with PXI timing?

I'm working in a lab that is trying to start to use a National Instruments PXI/VXI hybrid system. I currently know very little about timing and triggering. Basically all I know is that the timers we are using (PXI-6653) generate a square wave at 10 MHz and I can route it to the CLK10_in. I'm able to confirm that the clock is being routed there by using some of the example VIs and using a scope to see that the square wave is being outputted through the BNC connector on the back. I can see it's not the regular PXI 10 MHz reference clock because there is a difference in 10 MHz signals between before I hit the "GO" button on the routing VI and after I hit the "GO" button. So all in all, I can confirm I'm getting the 10 MHz signal routed to the CLK10 backplane signal.
However, my main question is how I can use that CLK10 signal on my DAQ cards? We are using PXI-4462 and PXI-6123 cards. I'm trying to use some of the example VIs given with NI-DAQmx. Is the "onboardclock" a timer that's on the DAQ card itsself? What about this sampleclock?
I've read through the examples and tutorials on the NI website, and they aren't very "newbie-friendly".
Thanks,
Michael

Hello Michael,
Thanks for posting on the forums! What you are trying to do is called reference clock synchronization. This is also referred to as Phase Lock Looping (PLL) to a reference clock. You will access this reference clock with a DAQmx property node as shown below.
Your PXI-4462 is a DSA device. This needs to be the Master device. Take a look at the Synchronization examples that ship with LabVIEW. Launch the NI Example Finder by going to Help»Find Examples. Browse by task to Hardware Input and Output»DAQmx»Synchronization»Multi-Device. The image above comes straight from the Multi-Device Sync-AI and AO-Shared Timebase & Trig-DSA.vi example. You can modify this example to suit your application. But remember, the DSA device needs to be the master.
You may be wondering what the Sync Pulse is for. In addition the the NI Example Finder, the NI-DAQmx Help is a great resource. Do a search for Sync Pulse, and you will find quite a bit of information about it as well as other useful things to know and consider with DSA synchronization.
Message Edited by RT4CY on 10-25-2008 03:06 PM
Rod T.
Attachments:
refclock.jpg ‏110 KB

Phase Locking the Up and Down Converter Modules

I am interested in phase locking the 5660 and 5670 modules, but from what I understand...this might not exactly be possible.
Using the 10MHz references...it seems that I can frequency lock the two together (i.e. - I can eliminate any phase error due to the two LO's drifting away from each other). However...am I correct in assuming that there is no way to actually access the individual oscillators such that I can remove the phase difference between them?
For example...if I want to measure the phase added by a DUT....I would have to measure the phase without the DUT...then meausre the phase with the DUT...then look at the relative difference in the two phase measurements (as calculated from the IQ samples). However, if I were to repeat this measurement by first measuring the phase without the DUT....then turn the generator off...then back on again....then measure the phase with the DUT...I'd expect to get a different answer, since by turning the device on and off, I have no idea or control over the phase relationship between the two devices.
Is this correct?
Finally...does simply connecting say, the 10MHz Out of the upconverter, to the Freq Ref IN of the downconverter automatically frequency lock the two together...or do I have to go into LabView and programatically tell the things which reference to use?
Thanks!
Brandon

Hi Brandon,
You are correct in what you are saying. The PXI-5600 and PXI-5610 Down/Upconverters each have their own synthesizers internally generating the LO signals for the mixers inside, and these LO signals cannot be exported from the modules. For these modules to be phase locked, they would need to share the same LO signals.
By sharing the 10 MHz reference you can achieve frequency lock where the phase difference between the two modules will stabilize, but the phase difference will not be zero - it will be some unpredictable phase offset which will not be increasing or decreasing (i.e. frequency lock). Whenever the 5600 or 5610 is retuned, the phase difference will also be different.
With regards to the 10 MHz signal, both use the same component for the reference so it doesn't matter which module you lock to the other as they are equivalent in quality. You do need to make a call in software to lock the destination module to the source module. If you are driving the PXI backplane with the source module, you'll also have to make a SW call to do this. This is very easy though, just look for VIs called Configure Reference Clock or something similar.
Regards,
Andy Hinde
National Instruments

GPS timestamping continously sampled data

Hi all,
I'm working on an application that samples 32 analog and 5 digital signals at a fixed rate of 4 kHz and I'd like to accurately timestamp each sample using a GPS time reference.
The timestamp accuracy should be better than 120 us. The application is written in C/C++ and uses the DAQmx C API.
The hardware I have available is the following:
* PCI-6224 card (A/D with 32 analog channels, lots of digital I/O and 2 timer/counters)
* PCI-6602 card (8 timer/counters and a 80 MHz clock)
* TrueTime XL-AK (model 600-000) GPS time reference, with serial ASCII output, IRIG-B timecode output and PPS (pulse-per-second) output.
Unfortunately my GPS is not equiped with a 1 MHz or 10 MHz reference output. Also the IRIG-B output is not easily useable because it is AM modulated on top of a 1 kHz carrier (therefore not compatible with a digital input and all 32 analog inputs have already been allocated)
I plan to implement this application by doing all timing generation on the PCI-6602 and doing all sampling (analog/digital) on the PCI-6224. A pair of counters is configured to do GPS timestamping as demonstrated in the document in this thread:
http://forums.ni.com/ni/board/message?board.id=250&message.id=8560
By routing the same sample clock and digital edge start trigger to all blocks that sample data (analog or digital), the data from all measurement tasks would be synchronised to each other. This would result in 3 streams of parallel data: timestamp values (second + sub-second count), analog data (32 channels) and digital data (say 32 bits for each sample).
However I suspect that the counter arrangement from the thread mentioned earlier does not produce *buffered* timestamps. This would make it impossible to use it as I just described above. Is this correct?
Does anyone know another solution?
I've been thinking about the following alternatives:
1) Sample the PPS signal at a higher rate to more accurately find out where the first sample in the current second starts. Then the timestamp for each sample can be calculated as Tsample = Tpps + Tfirst_sample + N/F, where Tpps = time (in seconds) of the last PPS pulse, Tfirst_sample = offset of first sample in the current second, N = sample number within the current second, F = sample frequency.
2) Same as above, but using buffered two-signal edge-separation measurement to get the offset between PPS and sample clock at even better accuracy.

Typically, (and sometimes necessarily), a sample clock signal used for counter measurements would be connected to a counter GATE pin. For the specific case of "encoder" measurement on the 6602, the Z-index signal must be physically wired to the counter's default GATE pin, so the sampling clock signal would need to be physically wired to the GATE pin of a different counter. Having wired the sample clock signal to a single GATE pin, both of the 2 counter measurement tasks can programmatically specify that their sampling clocks come from that single pin.
The M-series board offers more flexibility in programmatic PFI signal routing than the 6602. You can pretty much wire to any PFI pin and then programmatically specify which pin to use as Input (SOURCE) and which as Sample Clock (GATE). I still typically adopt the convention of using default pins whenever possible.
The terminology for counters can be a bit confusing. In my opinion, the old traditional NI-DAQ was a little more cryptic at first glance but much more consistent overall. The new DAQmx terminology tries to hide implementation details more, but in the process generates multiple aliases to the same pin assignment, depending on how you're using it.
A quick rundown. A SOURCE edge causes the count register to increment. Under DAQmx, this may be referenced as an "Input" or a "Timebase" terminal, depending on the measurement mode. When counting edges, it's an Input. When measuring period or frequency, it's a Timebase. Whatever it's called, the natural behavior at the counter hardware is to increment a count register on each active edge.
A GATE edge can cause a count value to be stored in the acquisition buffer. Under DAQmx, it may be referenced as a "Sample Clock" source when counting edges. When measuring period or frequency it may be a "Channel" or an "Input terminal." Again, whatever it's called, the behavior at the board level is to store an instantaneous count value into the data acq buffer on each active edge.
[There are exceptions, of course. The GATE pin is also used for "Pause Triggering", and can also be used to reset the count register for position measurement with Z-indexing enabled. And so on.]
-Kevin P.

How to lock sampling frequency for 5673 and 5663

Hello,
In general I'm trying to lock transmitter and receiver together. It seems easy to lock the carrier frequency, however no matter what I do, I seem to have a drift in my sampling frequency (on the order of 1ppm).
Is the sampling clock in the 5663 digitizer tied to the same clock reference as the LO? ... I didn't think I would need the TClk mechanism here since I don't care about delay ...
Any thoughts are greatly apreciated. Below are a few specifics.
I'm using the 5673 as transitter and 5663 as receiver. I've noticed the folowing:
1. When each are using a 'Reference Clock Source' = OnboardClock I have a noticeable carrier offset at the receiver (eg 5.8 GHz carrier has ~7 KHz offset) and this is fine.
2. When each are using a 'Reference Clock Source' = PXI Clock, with the chassis physically tied, I see no noticeable carrier offset at the receiver.
3. When 5673 is using 'Reference Clock Source' = OnboardClock, 5663 using 'Reference Clock Source' = ClkIn (ClkIn/Out physically tied), I see no noticeable carrier offset at the receiver.
Solved!
Go to Solution.

Hi Clayton,
The digitizer sample clock time base source is different from the Reference Clock source. I've copied a description below of the difference between the two from the digitizers help.
Clocking:Reference (Input) Clock Source:
Specifies the input source for the PLL reference clock.
Clocking: Sample Clock Timebase Source:
Specifies the source of the sample clock timebase, which is the timebase used to control waveform sampling.
Yes, the default configuration of the NI 5663 is for the NI 5652 to export its internal 10 MHz reference to the NI 5622 so that the NI 5622 and the NI 5652 devices are frequency-locked. The NI 5663 can also be configured to lock to an external (10MHz only) reference source. The NI 5663 can also be configured to lock to the PXI 10 MHz backplane clock. Locking to the PXI 10 MHz reference does not require a cable, but this configuration does not provide the same frequency and phase noise performance as the NI 5652 internal Reference clock. All of this information is provided in detail in the NI RF VSA Help. See the directory below:
Regards,
Travis Ann
Customer Education Product Marketing Manager
National Instruments

Computing Requirements in Multiple PXI Chassis System

I have acquired a two PXI Chassis system, each with their own embedded controller (PXIe-8108 and PXIe-8130). I would like to control all instruments (simultaneously) in both chassis from a central location (either a laptop or one of the embedded controllers). What is the best configuration for this and will using one controller have enough power to drive two fully populated PXIe-1065 chassis?
(I am aware of the different configurations for control (MXI, etc.) and am more concerned with instrument performance, data buffers become full quickly etc., in using one PC controller)
THANKS!

Hi JMU_ISAT,
The PXIe-1065 chassis uses a four link configuration where there is an x4 link going to slots 7, one to slot 8, another to slots 9-14. There are also an x1 link converted to PXI that goes to slots 2-7 and another x1 link converted to PXI that goes to slots 11-13 and 15-18. Each x4 link gives 1 GB/s of bandwidth and each x1 link converted to PXI will provide 125 MB/s of bandwidth. These bandwidths are theoretical maximums where overhead and chip design reduces the bandwidth somewhat.
The PXI-8130 has four x4 links with the four link configuration so it will be able to get the full chassis bandwidth. The PXIe-8108 has four x1 links which will limit the bandwidth to 250 MB/s for slot 7, slot 8, and slot 9-14.
To synchronize the measurements across both chassis you will need a timing and synchronization module such as the PXIe-6672 in the timing slot of each chassis. This will allow you to route the clock of one timing module to the other and then use that clock to override the backplane reference clock of each chassis. Now each module can use the 10 MHz reference clock to synchronize to each other.
In order to control both chassis from one controller, you can run windows on one controller and LabVIEW RealTime on the other controller allowing you to distribute code from the windows controller to the LabVIEW RealTime controller. The other method would be to run a MXI connection from one chassis to the other to daisy chain the chassis. Since the most you can get out of a single slot of the PXIe-1065 is an x4 link, this would limit the total bandwidth of the daisy chained chassis to 1 GB/s theoretical maximum.
I hope this information is helpful!
Andy K.
Applications Engineer
National Instruments

Synchronizing a 6289 with a 4461

I'm trying to output synchronized signals on a 6289 (analog and digital outputs) and a 4461 (only analog outputs) on a PXI chassis (a PXI-1031), but I've been having quite a bit of trouble getting the two devices to synchronize. The 4461 documentation indicates that this device can synchronize to a 10 MHz reference clock:
NI PXI-446X devices employ onboard PLL circuitry. The PLL circuitry locks the onboard 100 MHz voltage-controlled crystal oscillator (VCXO) to the PXI 10 MHz reference clock signal, PXI_CLK10. The VCXO output provides the source for the DDS chip, which generates the sample clock timebase. In this way the NI PXI-446X devices lock the sample clock timebase to PXI_CLK10.
However, I've been unable to access this reference clock directly; I can neither read from it nor write to it. Does this phase-locking occur automatically? If I route PXI_CLK10 to the reference clock input of the 6289, will the two cards be synchronized?
Since I haven't been able to assess whether using the PXI backplane's 10 MHz clock as the 6289's reference clock will synchronize the two cards, I've tried a number of other techniques without much success. The 6289 has an accessible sample clock timebase of 20MHz, while the 4461 has a sample clock timebase of 26.2144 MHz, so these seem to be imcompatible, even if a divisor is used. Additionally, the 6289 does not seem to accept Synchronization Pulses, so even if I could share the timebase (as one would do to synchronize multiple 4472s), the sample clocks on the two cards would be out of phase. If I try to share the Sample Clock directly, I find that the 4461 can only use its onboard clock for the Sample Clock, although I can export the 4461's sample clock to the 6289.
Is there any better way to synchronize these two cards? Thanks.
Jason Rolfe
Jason Rolfe

Rolfe,
The 6289 doesn't have any filters on the Analog Output, so the only filter delays you will have to worry about are on the 4461.
To synchronize the two devices, you have several options. I'll ignore the filter delay on the 4461 for now and come back to it later. First, yes you can use CLK 10 to synchronize both devices. To do this, set the reference clock source to CLK 10 on each device by using the timing property node. For this to work, you will have to have NI-DAQ 7.4 installed since CLK 10 synchronization support for the 4461 was added in this version of the driver. In addition to locking to CLK 10, you will also have to share a start trigger between the two devices. Since there is no trigger support for digital output on the 6289, you will have to use the 6289's ao/sampleClock as the do/sampleClock and start the digital task before the AO task. This solution is nice in that you can output at different rates on the two devices and still maintain phase relationship throughout time.
A second option to CLK 10, is to use the sample clock from the 4461 as the sample clock for the 6289. When using this scheme, you will need to start the digital output and AO task on the 6289 before starting the task on the 4461. This approach is a little more straight forward, but has the disadvantage that it forces all tasks to run at the same sample rate.
Now, we need to address the filter delay on the 4461. So far, the synchronization described above ensures the clocks are synchronized, but it doesn't account for the digital filter delay of the 4461. Depending on the sample rate of the 4461, this filter delay can be 36.6, 36.8, 37.4, 38.5, 40.8, 43.2, 48.0, or 32.0 samples (see the NI Dynamic Signal Acquisition Help for more detailed information). If you are running at a sample rate that doesn't have a fractional sample delay (or you don't care about the fractional delay if it's close enough for you), you have a couple of options. First, you can account for the delay in software by generating waveforms in the software buffers that are already offset by the appropriate sample delay. If you want a hardware driven solution, you can use a start trigger for the AO task on the 6289 and specify a delay from the start trigger of the appropriate number of samples. This can be done through properties under the trigger property node. Using the ao/sampleClock on the 6289 as the sample clock for the digital task will then delay the digital task as well.
If you want to get rid of the fractional delay, you'll have to use the CLK 10 synchronization approach as well as a counter to offset the start of the generations on the 6289 by the appropriate amount. To do this, you'll have to create a counter pulse train task that uses a start trigger. The frequency of the pulse train should match the frequency of the AO sample clock on the 4461. To correct for the filter delay of the 4461, you'll have to calculate the length of time of the filter delay and specify this value as the initial delay for the counter pulse train. The output of the counter is then used to clock both AO and digital tasks on the 6289. The start trigger for the counter task will come from the 4461. So the sequence of events is as follows: 1.) Start the counter, digital, and AO tasks on the 6289, 2.) Start the AO task on the 4461, 3.) The start trigger from the 4461 gets routed to the counter on the 6289, 4.) The counter waits for the initial delay to pass before outputting the pulse train, 5.) The counter starts outputting a pulse train of the same frequency as the sample clock on the 4461 for use by the AO and digital tasks, 6.) The signals on the I/O connector from all three tasks are now synchronized.
Let me know which approach you're leaning towards and I can futher clarify some things if you still have questions. By the way, what sort of application are you developing? I don't typically see this mixture of devices and I/O types.

MIMO vs 10 MHz Reference

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