MITE initialization of the 660x card

Question

The 6602 and 6608 cards require a slightly different initialization of the
PCI interface (MITE chip) on the card than other NI cards such as the E
series MIO. With this updated initialization of the MITE, there is no
problem addressing the second TIO chip (TIO1) on the card.
The E series cards include the following initialization of the MITE:
//Tell the MITE to enable BAR1, where the rest of the board's registers
are
Bar0.write32(0xC0, (physicalBar1 & 0xffffff00L) | 0x80);
For the 660x this should be replaced with the following code:
// ***** 6602/6608 specific MITE initialization *****
// Hit the IO Window Base/Size Register 1 (IOWBSR1) in the MITE. We set
the
// address, enable the window and set t
he size of the window:
Bar0.write32(0xC4, (physicalBar1 & 0xffffff00L) | 0x8C);
// Write to the IO Window Control Register 1 (IOWCR1) to make the IO
window
// go to RAM memory space instead of the config space
Bar0.write32(0xF4, 0);
physicalBar1 is the physical address of BAR1on the card which is the base
address of the TIO0.
Bar0.write32 writes to the given offset from BAR0 which is the MITE chip on
the board.

Answer 1

The information about the MITE initialization above supercedes the information in the April 2002 (or earlier) edition of the 660x register level programming manual. The manual is in the process of being updated and will be posted soon.
Christian L
Consulting Services - RLP
National Instruments
Christian Loew, CLA
Principal Systems Engineer, National Instruments
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