Multiple fpga vi's with same interface, single RT vi

Hi everybody,
I'm using a crio system to control as experimental setup. In this setup several types of tests can be done and for each, basically the same control is done, but the returned data is different. Therefore i wrote several fpga vi's with the same controls on the interface, and a DMA fifo to transfer the data. I've also written a subvi for my RT system which reads the data from the DMA fifo and transfers it further downstream for analysis. This RT vi has to be rewritten for each FPGA vi as the FPGA vi references are incompatible. How do i make the subvi generic for all these FPGA vi's? The DMA fifo is the same, as is the type and amount of data...
looking forward to your suggestions,
Daniel Lindenaar

Hello Daniel!
I am not sure which FPGA target you are currently using but one method to achieve what you want it to use the Up Cast method. If you use cRIO you have an example called ‘Using the Upcast Function - cRIO.lvproj’ and if you use R-Series look at the example called ‘Using the Upcast Function - R Series.lvproj’. Hope this helps and Merry Christmas!
Regards,
Jimmie Adolph
Systems Engineer Manager, National Instruments Northern Region
Bring Me The Horizon - Sempiternal

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Attachments:
question.png ‏76 KB

Intaris
Trusted Enthusiast
Posts: 3,264
Re: LabVIEW FPGA: Multiple SCTL versus one SCTL (same clock domain)
‎10-28-2014 12:11 PM
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Device Utilization
Total Slices: 17.6% (2587 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.2% (4855 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
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Total Slices: 16.9% (2493 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.3% (4858 out of 58880)
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Total Slices: 16.4% (2407 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
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