Multiple timed loops in RT interface- initialization, communication

Problem Description :
I am attempting to deploy an adaptive control system using cRIO. I have an NI
9505 that controls a motor, and triggers other part of the machine to produce
data. I get data in my control loop and perform on-line estimation (currently)
using RLS estimator.
I have two-fold trouble
1> My Motor control and data acquisition is on one FPGA VIs and data filtering
and Estimation algorthon is on the other FPGA VI. I am supposed to call both of
the FPGAs in my RT interface VI with necessary operations.
Problem 1: How to simultaneously call two FPGA VIs in separate timed/while
loops in my interface VI?
2> Note that these two loops are supposed to talk with each other, once
estimation VI produces new coefficients, they are to be fed back to control VI,
I am not sure how to perform this.
It's kind of time critical that I accomplish this , Please help.
Thanks,
NI Software : LabVIEW Professional Development System version
NI Hardware : CompactRIO device

Because of the nature of FPGA, you can’t call two FPGA VIs at the same time. When you call an FPGA VI, you load up an FPGA bit file and physically reconfigure the FPGA chip. The FPGA chip can only be configured for one bit file at a time, so simultaneously calling two files at once will not be possible. If you need to perform functions from both VIs simultaneously, you could try combining them into one master VI that contains the functionality of both VIs. You could then pass information to and from each RT loop to the appropriate section of FPGA code. Keep in mind that FPGAs are a finite resource, so you’ll need to make sure that this new larger FPGA VI still fits on your chip.
Hope this helps answer your questions!

Similar Messages

Limited sampling rate with multiple timed loops

I am trying to use two timed loops. The first timed loop is supposed to acquire some analog inputs, average the values, and then display the average values on the Front Panel at a rate of 2 Hz. When I want to acquire data I enter a second timed loop and try to acquire data at a rate of 50 Hz. The second timed loop is designed to acquire 1 value and then append the data to a file. During the 50 Hz acquisition I want the first timed loop to also run so that the Front Panel continues to refresh values at 2 Hz.
The problem I'm getting is that the second timed loop doesn't acquire and write data any faster than the first timed loop. So in this case I'm limited to 2 Hz data acquisition when I want 50 Hz.
Attachments:
SWIFT_Dive Record2.vi ‏270 KB

Hi FRLFTE,
the second loop run not faster because both loops are in the same "big" while loop, so that the second loop has to wait till the first is ready.
Mike

Write to XML File crashes when multiple Timed Loops present

Hello All,
It took me forever to track this bug down.
In this project we can edit operating parameters on the Host and send them down to an RT program in a cRIO-9025. The data is converted to XML and stored on the cRIO's disk.
Occasionally, the RT program would lock up and had to be rebooted.
It turns out that if you use Timed Loops , then a Write to XML File (or presumably any file write) will not return.
Attached is an example. This has 5 loops to make it crash faster, but it will eventually crash with only 2.
Paul J
Attachments:
XML Write test.vi ‏93 KB

Hello Chris,
I know that Write to XML File fails because I put in debug code in my actual program, a flat sequence which updated an indicator, and after the crash, the indicator had not updated.
Yes, I know that it replaces the file. It's a configuration file, not data gathering. This is just an example of the bug.
FYI,
I increased the period for the loop with the file save to 500msecs and it still crashed.
I then decreased it to 50 msecs, and replaced all of the other Timed loops with While loops and it does not crash, even though the file save takes much longer than 50 msecs, average ~150msecs.
I replaced the loop with the file save with a While loop while leaving the others as Timed loops and it does not crash.
So the bug is systemic and related to a file save in a Timed Loop when there are other Timed Loops.
I'm not looking for a solution, I'm only reporting a bug in Labview. The solution is not to use Timed Loops, especially, as you point out, when there is file saving. It cost me several days of dicking around to figure it out. Maybe someone can save some time if they find this.
Paul J

Multiple timed loop question

I am currently in the planning stage of a medium sized labview application and I need some help figuring out the best approach as application of this size is still new territory for me.
I have a daq device monitoring 4 channels, a couple of motor controls, and the goal is to update the GUI with the information from the 4 channels, and also calculations performed on that information, all while letting the user control the motors in real time. All actions and data will be logged and written to disc preferrably in real time.
The plan so far is of course to beak them up into subVI's, with the motor controls in 1 subVI, and the monitoring in 1 subVI, calculation performed on the data in another subVI, and a main driver VI that controls the timing of the loops and updates the GUI.
I initially thought about using action engines for the data acquisitions, but I realized that using action engines might "freeze" the program when data acquisition is happening, and the user will lose control of the motors. Another approach is the producer/consumer pattern, where the incoming data from the DAQ is consumed to perform calculations and the data logged onto disc. This is the approach that I think I will take, but how do I implement the real time motor controls into this pattern?
The idea that I have is to have a main program state machine that handles all user input, and parallel loops that implement the producer/consumer model, and another parallel loop that will update the motor information when it is changing. Is this a suitable approach for an application of this type? Would a queue help the timing aspect in between the parallel loops? As calculations must be performed on each iteration and updated to the gui before the next data point is acquired, at the speed of 100hz. I am having trouble visualizing how to implement multiple loops in separate subVI's and synchronizing the data in between each other.
Please advice if there are other better patterns/approach for something like this.
Thank you.

Producer consumer would fit here well. You will also need to use a state machine system for flow control. I would also look into event structures and firing events. If you put all of this together it will make a nice simple upgradable program. This is a system that I helped somone else start.
Tim
Johnson Controls
Holland Michigan
Attachments:
Try This System.zip ‏84 KB

Unable to run Timed Loops

Bit of an odd one that had me scratching my head.
I have a development system consisting of a PC running a 7842R, acquiring analogue and digital data from the FPGA, loading it into a shared variable, and reading it out within a timed loop on the host as one parallel loop in a producer-consumer architecture.
All's well until one day last week when I noticed my host VI becoming unresponsive.
After a bit of digging, I find that the timed loop doesn't run at all. Replacing with a while loop with a wait at least allows me to show that the error is timed loop related, but it's not a viable long term option for me. Creating a new project and a new VI with a simple timed loop showed the same behaviour.
A restart of the system, and rerunning the same VIs, and no problems since.
So, questions:
1) Has anyone else seen this behaviour?
2) Any idea what causes it? A service crashing, for example?
3) Is there a way of recovering without a reboot? If it's a service crash, I'm hopeful.
The system will eventually form part of a production test environment, hence the query.
Edit - also, wiring error terminals of a timed loop is a good way of highlighting errors of course.
FWIW, LV2012 SP1 32bit, Win7 64bit, Core2 Duo, 4GB RAM, tassels from the handlebars etc.
CLD

The timed loop is used to read all elements from a DMA FIFO and load them into a buffer FGV, which spits out packets of N samples long once they've assembled within the FGV. Ordinarily, I'd do this with a timed while loop and be perfectly happy to do so. However, the elements are actually an interleaved array, meaning that I have to demux them in the correct order that they were loaded.
I use timed loops for a number of reasons: on my current Windows host, I've found that using a while loop has caused me more problems with respect to disordered packets, and that at least with using multiple timed loops (two, at most), I can assign priority to the acquire loop. Finally, it's also a development platform, and will be deployed onto an sbRIO once the electronics integration is finished in a week or two!
W.r.t. system resources, there's very little else running on that system, but that doesn't normally stop Windows
I recognise it's not ideal to run a software timed loop under Windows, but when you cannot run a blank project with Optimizing timed loop rate.vi from the shipped examples with nothing else running, it makes me curious to know why!
CLD

Why does a CRIO-9004 only provide a timed loop of 1kHz (clock) and not 1MHz?

I essentially have a compact CRIO-9004 and require a PID loop with update rates around 4-5 kHz. Additionally, I was hoping to use multiple 'timed loops' in the program in order to synchronize certain events. During this coding, the timed while loop will not work with a 1MHz clock rate and I am stuck with a clock rate of 1kHz instead. NI claims that PID loops in conjunction with the CRIO may have up date rates as high as 200 ksps. However, it appears that by employing the 1kHz clock that I can only obtain 1 ksps.
What are my options?
Thanks,
Shane

John-
The 9215 has a conversion time of 4.4us when scanning 1 channel (see page 14 of the 9215 operating manual). This equates to a little over 227KS/s. The 100KHz value is if you are reading from all 4 channels.
Link to operating manual:
http://digital.ni.com/manuals.nsf/websearch/5F2E9640C1CFE645862573AF007ABAD9
Dustin
Message Edited by Support on 10-16-2009 09:16 AM

How do I associate timing with multiple AI loops that is independant of loop execution speed

I am using Labview 7.1 and I am performing AI of
voltage on different channels of the same multifunction DAQ. I am
using while loops to aquire the data. I am writing the data to
spreadsheet file with an associated time as a 2D array. Currently I am
using the 'elapsed time' interactive subVI to get the time in seconds
(attempting to use the 'Get Date/Time in seconds' and converting it to
DBL results in time values that do not change. My thoughts are that
maybe the number of seconds is too large to display single second
precision with a DBL floating point number). When I run AI on two
multiple loops they execute at different rates and thus the time values
from "elapsed time" are accumulated at different rates. I have tried
using timed loops to control timing, but if one loop executes at a rate
slower than the timing of the loop the 'elapsed time' still accumulates
at different rates. I need to be able to associate both analog inputs
to the same time
value in the spreadsheet value and I would like to find a way to
associate a time with each data point that is independant of loop
execution speed (although I would still like to control execution speed
of the loops. I am pretty new to Labview and programming in general,
any help would be greatly appreciated.

If you want to read more than one AI at the same time, you should use a trigger. You would need to set up the AI Trigger to an external source. Then you would have to use a function generator or digital out to create a clock. The clock would be wired to the AI external trigger. When the clock goes high (or low depending on configuration), both AIs would read. That is the method I use when needing to sync multiple AI inputs.
- tbob
Inventor of the WORM Global

Shared variables + timed loops + naming conventions + how to find all

Being almost halloween, thought I'd share some more eerie behavior I've noticed with shared variables.
1st strangeness with timed loops already mentioned here: http://forums.ni.com/ni/board/message?board.id=170&message.id=209475
2nd strangeness: If you have a shared variable that is network-enabled, it is OK to use a "?" in the name (eg, "RT_Simulate?").
However, should you decide to change that variable to single-process, or if you create it that way in the first place, you will get this dandy message from the broken arrow you now have:
"LabVIEW could not generate code for the shared variable. You must open the VI in the project that contains the library where the shared variable resides."
..............whaaa????? Loosely translated, this seems to mean "Don't use a "?" in your single-process variable names."
3rd strangeness: I don't know if this has been mentioned before....
If you have an application that references a network shared variable, and the library has NOT been deployed, the app will hang for some time (approx. 7 seconds! on my machine) before returning with an error. This seems to be the case whether or not the error ins/outs of the variable are wired. This looks bad to me, and I'm not sure what is causing it (some sort of timeout when attempting communication with the SVE I assume). Has anyone else noticed this? It should be easy to reproduce. Any ideas?
I haven't done any bug notifications yet, but will do if there are no positive solutions by next week some time.
-Have a Great Halloween Weekend

WHAVEman,
Currently (as of LabVIEW 8.20) there isn't a way to programmatically interact with the shared variable engine outside of using DSC. If you had DSC you could "hack" a way to determine if a shared variable was deployed.
I think the best way to get around your program hanging is to have an initialize state where you write a dummy value to each variable. If the variable isn't deployed, then you should get an error out of the shared variable. Problem is that there's probably going to be a timeout associated with determining if the shared variable is deployed. But at least you can use the information from your initialize state throughout the rest of your deployed application.
Chris C
Chris Cilino
National Instruments
LabVIEW Product Marketing Manager
Certified LabVIEW Architect

Timed loop and CPU usage

Platform is WIN_XP Pro and machine is a P4 at 2.5Ghz with 512 Mb ram.
LV7.1 + PCI 6229
I am using 50ms Timed loop for running a state machine inside it
and also a whole lot of other things like reading / writing
DAQMx functions; file I/O functions and such. As the
project involves a main and sub-panlel set up local variables
could not be elimnated fully and there should be something like 150 of
them. But not all are accessed always - maybe about 15 of them at any
given time depending on the SM staus.
Problem :
Once started the "Finished late" indication is off and
the actual timing alternates between 49 to 52 ms. The CPU
usage is around 25%.
But as time goes by, the system gets unstable : After 15 minutes
or so, the Finished Late indication is always ON and the CPU usage is
gradually tending towards or exceeds 100%.
Obviously the machine control timing now gets affected and things slow
down badly. Closing the application ands restarting repeats the above
cycle.
I am at a loss to understand what is happening ? WIll
breaking down the single Timed Loop to multiple ones help ? WIll
that be an efficient way of parallel threading ?
I can post the code but its quite large and will do it as a last resort.
thanks
Raghunathan
Raghunathan
LV2012 to Automate Hydraulic Test rigs.

Hello,
It sounds like an interesting problem. It would be worth some experimentation to figure out what's going wrong - attempting to decouple major "pieces" of the code would be helpful. For example, you could try breaking your code into multiple loops if that makes sense in your architecture, but perhaps you could even eliminate all but one of the loops to begin with, and see if you can correlate the problem to the code in just one of your loops.
Another concern is that you mention using many local variables. Variable read operations cause new buffer allocations, so if you're passing arrays around that way, you could be hitting a problem of forcing your machine to perform many allocations and deallocations of memory. As arrays grow, this can be a bigger and bigger problem. You can use other techniques for passing data around your block diagram, such as dataflow if possible (just simple wires), or queues where dataflow can't dicatate program flow completely.
Hopefully looking into your code with the above considerations will lead you in the right direction. In your case, removing code so that you can identify which elements are causing the problem should help significantly.
Best Regards,
JLS
Best,
JLS
Sixclear

Questions about parallel and series sturcture in SCTL (single clock timed loop) in FPGA VI

I am using LV 8.2.
I have wriiten a FPGA VI, in this VI, there are 3 filters inside the SCTL (single clock timed loop) (I use the shift register to be the effect of unit delay). Would I save the resources of the FPGA used (such as slices and LUT) in the compliation report if I use 3 SCTL ( 1 SCTL contain 1 filter) and cascade them in series?
Thank you!

Sorry, I am afraid that you have misunderstood my meaning.
Here is the method you suggested before:
I mean I use the shift registers attached in the while loop, not in the SCTL. The number of shift registers used will not be decreased when we increase the number of SCTL in the second plate of the flat sequence structure. Totally , there are 6 pairs shift registers for 3 filters (1 filter needs 2 pairs). I mean I put the calculation parts, such as b0*x[n]+b1*x[n-1]+b2*x[n-2] inside the SCTL ( the operations of multiplication and add). Instead of putting 3 filters numeric operation part in one SCTL. will we reduce the resources used if we use 1 SCTL to do the operation parts of 1 filter? As the code inside each SCTL will be reduced.
Maybe you tell me if such approach will reduce the reosources used? Or there is no difference?
Thank you!

LabVIEW RT, Timed loop, finished late, Call by reference

I have a timed loop triggered by the sample clock of a DAQ-Card. The sample Clock is 8 kHz and the loop will run with dt = 4. Normally the loop is running without finished late[i-1]. But from time to time it happens that the loop is running extremly longer which means instead of 0.5 millisec it needs 4 - 5 millisec. It seems this doesn't never occur while accessing DAQmx.
The application uses plugin technologies and some of the VIs in the timed loop are preloaded and called by Call by Reference.
Does those VIs inherit the priority, execution system and CPU of the timed loop?
The application is running on LV RT 2009 on a Dual core PXI-Controller. The timed loop is bound to CPU 1. There is no difference runinng the application from the development environment or as a startup application.
For the measuring test I modified the application in a way that I don't have:
disk access for storing the result file
TCP/IP communication
Controls on the front panel of the top level VI
Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

To keep you informed:
I stripped the application and have left only the measurement storing module and the timed loop. The loop was using the microsecond timer running each 500 µsec. Additional all Non-Real-Time modules were loaded and only one module creates a XML string and sends it to the communication layer which will drop it because no TCP/IP port is open. The creation of the XML string is done each 300 ms.
In this case I don't have any finished late iterations
Next I added the DAQ Module. Now I get finished late again but with a lesser frequency as original.
I removed all unnesseccary tasks from the DAQ moulde leaving one task for a PXI-4204 for using as the clock source for the timed loop. No I get finished late seldom.
I removed the module which will send the XML string and I don't get finished late.
Next I was adding code to see memory allocation. I can when memory allocation is changing but it is not related to the finished late iterations.
Next time I have the chance to do more tests I will see which DAQ task triggers the finished late iterations. I have one AI task on a PXI-4204, 4 Counter tasks on a PXI-6602, 1 DI task on a PXI-6514, 1 DO task on a PXI-6514, 1 DI task on a PXI-6259, 1 DO task on a PXI-6259, 1 AO task on a PXI-6259 and 1 AO task on a PXI-6711.
The AI task on the PXI-4204 is running in Continous Sampling (Single Point HW Timed is not supported), all other tasks exept the DI and DO are Single Point HW Timed.
Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

Timed Loop in Producer/Consumer Loop

Hello!
I have a producer/consumer loop LabVIEW program setup to allow me to properly capture images that are quite large (8MP) at approximately 14 frames per second (FPS). The program works great when the consumer loop is a 'while loop' (records at 14fps no problem), but I wanted to make it into a timed loop, so that I may vary the FPS as required. An oddity arises when I do this. Anywhere below 12fps, the loop works fine and the data is recorded properly. However, when I bump it up to 13fps, the consumer calculated FPS goes haywire and starts jumping between ~9 and ~13fps (data processing gets bogged?). When I set the required FPS to 14, the loop executes at a steady 7FPS maximum. Is there something I can do to rectify this situation?
I have attached my .VI
Thanks in advance!
Solved!
Go to Solution.
Attachments:
ProcessSplitJPG-FPS.vi ‏100 KB

Palanski,
Are you using LabVIEW Real-Time? Timed loops in a windows OS don't really increase determinism more than a while loop with a wait until next multiple timer. Before you changed the producer consumer loop to include a while loop was the programming running correctly? You may also want to vuse the VI analyizer to see how long things are taking to run. I would leave the producer consumer loop in the traditional set up and change the FPS by controlling the wait timer, after benchmarking your code this should be done the same way as you have it for the timed loop
Sam S
Applications Engineer
National Instruments

Timed Loop timing source - Control Loop From Task is too slow

I'm trying to make a Timed Loop run at a period of 2 ms, with an analog input task running at 50 kHz as timing source. The input analog signal is scaled and fed into a synchronised analog output task on the same multifunction DAQ board. Using the built-in 1 kHz or 1 MHz clock as timing source for the Timed Loop works great, except for a slight time lag between the loop and my AI/AO tasks which over time becomes unacceptable because my task will be running for up to an hour. However, when I use the DAQmx Create Timing Source: Control Loop From Task vi to create a timing source, everything slows down and the fastest loop time I can get is around 20 ms. Any suggestions to get around this would be highly appreciated!
System: LabVIEW RT 8.0 with DAQmx 8.0 running on an NI PXI-8186; NI PXI-6251 used for analog input.

You're welcome!
You can build an array, and if your data is not hugh (100's of MB) this may be the easiest solution. However, we aways suggest implementing the Producer/Consumer Architecture. Keep the PID in the Producer loop, but move the File IO to the Consumer. Also, it appears that your instrument uses some form of serial communication, so that could cause lags in your system....
What is your application about in general, what performance are you hoping for, etc?
Joshua B.
National Instruments
NI Services
NI Support Resources
NI Training Resources

Memory leak in Real-Time caused by VISA Read and Timed Loop data nodes? Doesn't make sense.

Working with LV 8.2.1 real-time to develop a host of applications that monitor or emulate computers on RS-422 busses. The following screen shots were taken from an application that monitors a 200Hz transmission. After a few hours, the PXI station would crash with an awesome array of angry messages...most implying something about a loss of memory. After much hair pulling and passing of the buck, my associate was able to discover while watching the available memory on the controller that memory loss was occurring with every loop containing a VISA read and error propogation using the data nodes (see Memory Leak.jpg). He found that if he switched the error propogation to regular old-fashioned shift registers, then the available memory was rock-solid. (a la No Memory Leak.jpg)
Any ideas what could be causing this? Do you see any problems with the way we code these sorts of loops? We are always attempting to optimize the way we use memory on our time-critical applications and VISA reads and DAQmx Reads give us the most heartache as we are never able to preallocate memory for these VIs. Any tips?
Dan Marlow
GDLS
Solved!
Go to Solution.
Attachments:
Memory Leak.JPG ‏136 KB
No Memory Leak.JPG ‏137 KB

Hi thisisnotadream,
This problem has been reported, and you seem to be exactly reproducing the conditions required to see this problem. This was reported to R&D (# 134314) for further investigation. There are multiple possible workarounds, one of which is the one that you have already found of wiring the error directly into the loop. Other situations that result in no memory leak are:
1. If the bytes at port property node is not there and a read just happens in every iteration and resulting timeouts are ignored.
2. If the case structure is gone and just blindly check the bytes at port and read every iteration.
3. If the Timed Loop is turned into a While loop.
Thanks for the feedback!
Regards,Stephen S.
National Instruments
Applications Engineering

Timed loop not starting - works after closing and opening project

Refer the image below - a simple timed loop should run when the Run button is pressed. What happens is that the parallel vi runs (see arrow) but the vi inside the loop doesn't. Both vi's shown run forever (i.e. the timed loop is only used to specify the CPU).
When I press the Abort Execution button, strangely it can then be seen that the execution highlighting runs into and through the timed loop and probe 50 is updated.
This sorted itself out after I closed the project and opened it again so its not a critical issue - was simply wondering what could cause this?

That program looks kinda weird.
First of all, avoid to use flat sequence structures whenever you can, or use it only when you are going to initialize something, or when your program has an specific sequence.
I think you have a problem the way you are conecting the subvis. Remember that in LabVIEW, the flow of the data will determine the order of execution, and in your case, the conections looks kinda weird.
I have a question; Do the subvis need to run simultainously?, or what do you need to do exactly

Multiple timed loops in RT interface- initialization, communication

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