Partial dma problems on x86 (intel)

Question

Hi,
I am trying to port a Sparc driver to x86. On SPARC, you have DVMA, so
essentially SGlist size is 1. On x86, you get a large SGList. Our h/w can
handle only 64 SGL entries. I keep messing with just about every parameter
in ddi_dma_attr struct, but no luck. I or'ed in PARTIAL_DMA flag, but it keeps giving me 64+ cookies.
I have loaded latest patch cluster as of 4/19/00, but does not help.
Please help.

Answer 1

Hi Harish,
Following is the excerpt from one of FAQs.
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For our discussion we are focusing on the number of scatter gather elements only. This is controlled by the dma_attr_sgllen member of the ddi_dma_attr structure. A popular misconception is that the dma_attr_sgllen is the maximum number of cookies the ddi_dma_alloc_handle() will return. This is not true. The ddi_dma_alloc_handle() will return as many cookies it needs to satisfy the request.
Let's see an example. Assuming you want to do a DMA transfer of lets say 1MB and your hardware can handle 64 scatter gather elements. So you would call the ddi_dma_alloc_handle() with dma_attr_sgllen set to 64. In this case let us say that ddi_dma_alloc_handle() could not fit in 1MB into 64 contagious memory segments. Then it will return lets say 96 cookies. The sum total of all the sizes of the 96 cookies will be equal to 1MB and the first 64 cookies will satisfy all the alignment requirements that you had requested in the ddi_dma_attr structure.
The device driver is expected to check for this condition and handle the transfer using two or more dma requests to the DMA hardware. As each set of 64 cookies satisfy all you alignment requirement it should be just doing multiple 64 scatter gather element dma transfers.
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Hope this helps.
Thanks
Kalpesh