PetaLinux vs Vivado SDK?

Can someone explain the difference between PetaLinux and the Vivado SDK for linux development? As far as I can tell, the Vivado SDK contains all of the build tools needed to build linux applications (arm-xilinx-linux-gnueabi-*). What's the difference between manually building linux-xlnx and u-boot-xlnx from the Git repository vs using PetaLinux? What's the prefered method to build and setup a linux development enviornment?
I've installed Vivado SDK on my Ubuntu Machine; git cloned, configured, and built u-boot-xlnx and linux-xlnx. Everything seems to be working fine on my Microzed board. Are there any advantages to using PetaLinux?

PetaLinux is our full Linux distribution which includes the Linux OS as well as a complete configuration, build and deploy environment for Xilinx silicon.PetaLinux Tools provide a simple and fast method to build and deploy Linux-based software on Xilinx Zynq-7000 APSoC and MicroBlaze devices.
Although the PetaLinux kernel is based on a stable and thoroughly tested Linux, also from the Xilinx Git server, PetaLinux offers much more than what can be downloaded from our Git. PetaLinux includes installer, development tools, BSPs, platform management utilities, application and library frameworks and documentation that are not found within our OSL offering.
With PetaLinux, you can:
• Build and configure Linux components; Linux kernel, u-boot and file system, for Zynq-7000 APSoC and MicroBlaze based designs
• Easily synchronize your Linux software platform and hardware platform in a single step
• Easily target and migrate your Linux user application to Zynq-7000 APSoC or MicroBlaze based Linux platform
• Quickly get started with building Linux-based software on Xilinx and partner development boards using the pre-built Board Support Packages (BSPs)
• Test your Zynq-7000 APSoC or MicroBlaze Linux system without any hardware in a virtual machine environment using QEMU
You can refer to the design flow details in the link http://www.wiki.xilinx.com/PetaLinux+Getting+Started
For more details refer to the Petalinux Documentation.
Regards,
Achutha

Similar Messages

There is a missing letter of Path name or file name when vivado SDK linking object files

I used vivado SDK 2014.3 to complie the third source code and could get *.o files. But when linking them, there was an error to show that No such file or directory. I found that there was lack of letter in path name of object file. It's a SDK bug or I don't set up correctly?
Thank you for an early answer.

I tried it in vivado SDK 2015.1, but there was still the same problem. And I found that it was successful if only importing a small part of source code. What is the reason for this situation?

Generate device tree Vivado/SDK/HSI 2015.2

1) Clone git://github.com/Xilinx/device-tree-xlnx.git to device-tree-xlnx
2) Export Hardware from vivado 2015.2
3) Launch SDK 2015.2
4) Add cloned device-tree-xlnx folder to repositories in SDK 2015.2
5) From SDK, File->New->Board Suppor Package. Select device_tree from Board Support Package OS options. Click Finish
6) The following error is displayed in the SDK log:
****** hsi v2015.2 (64-bit)
**** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
   ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
INFO: [Hsi 55-1698] elapsed time for repository loading 0 seconds
ERROR: [Common 17-161] Invalid option value '' specified for 'object'.
ERROR: [Hsi 55-1545] Problem running tcl command ::sw_device_tree::generate : ERROR: [Common 17-161] Invalid option value '' specified for 'object
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   (procedure "get_baseaddr" line 4)
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       gen_r..."
   (procedure "::sw_device_tree::generate" line 3)
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"::sw_device_tree::generate device_tree"
ERROR: [Hsi 55-1442] Error(s) while running TCL procedure generate()
ERROR: [Common 17-39] 'hsi::generate_target' failed due to earlier errors.
----------------------

Hi,
After lookming at my work in the morning, I am afraid the solution requires alot more work than I am willing to delve into. At the very list I can help you with a work around.
In the IP packager
1) Remove IIC interface or other broken interface.
2) Select all ports that used to be grouped in 1) above, right click and select "Create Interface Definition"
3) If the selected ports are part of an input interface (left side of IP) select Slave Mode, and set location to be where your ip is. NOTE! after clicking ok, at the next prompt to create the Interface select NO unless it is one of kind IE you dont need an inteface opposite of the one being created due to selection of pins.
4) Select each port and hopefully your IP follows some of Xilinx's naming conventions e.g one of my IIC ports is int_sda_i and rename it to sda_i. Basically all other data is entered for you, you just have to fix the names of all the ports. This is import for the Auto Infer ports function.
5) save the interface. Do not close it yet. I don't know how to open it again if you need to adjust anything.
6) Now go back to Ports and Interfaces on the Package IP tab and slect the ports you previously selected. Right click and select "Auto Infer Interface"
7) Now go to the User tree and select your Interface definition. It is named what you set it to be in 3) above. Click OK
8) Give your IP a name and set interface presence as desired. As a side note, the example "$my_num_var > 0" does not make it clear that the variable my_num_var is created in "Customization Parameters"
9) If applicable, select the port for the other interface eg output iface and repeat 6), 7), 8)
10) The bad new is that on the side that interfaces with Xilinx IP block e,g IIC_1 on a processing system block you have to wire it up manually but at least you can gropu that mess into a hierachy. The good news is that the other end can be made "external" on the BD so you don't have wires all over the place.

Vivado SDK 14.1 MAKE file errors

I just installed Vivado 14.1 on a Windows 7 machine into the default C:\Xilinx directory.    Vivado seems to run ok but when building a BSP in SDK I get the following error for every IP in the design:
    "Compiling uartns550"
    mb-ar: ../../../lib/C:\Program: Invalid argument
     make[1]: *** [libs] Error 1
     make: *** [microblaze_0/libsrc/uartns550_v3_0/src/make.libs] Error 2
It looks like the make file is trying to read the 'C:\Program Files' directory and can't handle the space, but no part of the project or other software tools are in that directory.

Hello
I have the same problem. How can I fix it?
Thanks!

Regarding Vivado and xilinx ISE

Hello
I am working with VC707 board, so I want to know which is better either Xilinx SDK or Vivado SDK because i am getting .elf file error at the time of compilng my application.
Thanks and Regards
Antriksh

Hi,
With Vivado the implementation Algorithms are advanced and different than ISE.
The strategies available in Vivado invokes the algorithm at backend and try to give you better performance with respect to timing, placement and resource utilization.
Vivado has better capability of handling 7-series devices than ISE.
Thanks,
Yash Palorkar
P.S. ISE is good till 6-series devices :)
Thanks,
Yash

IntcSelfTestExample constantly FAILS

Vivado/SDK 15.1
Artix7 (xc7a200tfbg484-2), custom board, Microblaze 128K, 3xAXI timer, XADC, I2C, QSPI, 2xGPIO (1 IRQ), UART Lite, No cache, No MIG, 1xAXI Intc, 1 MDM, 80MHz.
8 IRQ lines concatenated into the AXI Intc. AXI Intc output is rising edge.
Running default generated Testperiph application.
1. If Timers are not initialized prior to IntcSelfTestExample, XIntc_SelfTest() fails to clear IRQs initially.
2. If timers are initialized first, then XIntc_SelfTest() fails to set the dummy test IRQ later on.
3. IntcInterruptSetup() also consistently fails.
3. No other peripheral test succeeds.
If I comment out IntcSelfTestExample() and IntcInterruptSetup() from testperiph.c and manually implement IRQ initialization sequence given in SpiIntrExample(), then all tests succeed (except IntcSelfTestExample() and IntcInterruptSetup()).
Rebuilt from scratch several times just to make sure, verified all connections in block diagram. Restarted SDK flow from scratch several times to insure good HDF files.
I have used Microblaze MCS before with no problems on Spartan3E. But SDK will not let me use MCS system with the Artix7.
I notice the IRQs are a mix of rising-edge and high-level IRQs. Does this cause problems? Is there some initialization step I'm missing?
It takes 5 hours for each H/W generation. Does this sound like an H/W or S/W issue? I have not found anything similar on the board.

Anyone have any suggestions on what to look for? Why would the interrupt self-test fail?

How to design block diagram for axi tpg and axi vdma on zedboard using vivado 2014.4 and sdk c application

Hi,
I am working in image processing project ,but currently i want to use tpg ip and vdma ip to write frame data in ddr3 on zedboard,please provide me vivado block design and sdk c application for that

Please don't post the same thing multiple times. This one is fine:
http://forums.xilinx.com/t5/New-Users-Forum/how-use-axi-tpg-and-axi-vdma/m-p/638588

Unable to create a new hardware platform in SDK from Vivado

I have exported a simple Vivado 2015.1 Hardware design to SDK 2015.1. I then open SDK to the correct workspace and take the following steps:
1) File -> New -> Application Project
2) I then name the project and click "New..." to choose the exported hardware platform from Vivado.
3) I then name the hardware project and browse for my hdf or xml file.
4) I select the .hdf file and click finish.
5) The dialog box does not go away.
6) I then click "Cancel" and can see that my harware platform is still not an option to choose from.
What could I be doing incorrectly?
Thanks for the help!

Hi,
You can refer from page 27 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug940-vivado-tutorial-embedded-design.pdf to understand the export to SDK flow,
Regards
Praveen
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

Error installing PetaLinux SDK

Hello,
I get the following error when i run the petalinux installer:
INFO: Installing PetaLinux...
./petalinux-v2014.4-final-installer.run: line 131: /tmp/tmp.XInB9FfGMx/petalinux-v2014.4-final/tools/common/petalinux/utils/petalinux-install: No such file or directory
I'm running Ubuntu 12.0.4 64bit Client on a VBox with a Windows 7 64bit host.
Does anyone know why this is happening and what I can do to fix this?
Thanks,
Gary

Hi Gary
I am running into this isue too.
Did you get an answer to this question?
Thanks
Eddy

Make to compile the Petalinux software image, but "returned an error code (127) ;make[1]: *** [pkg_stagefs] Error 255"

Hello,
I am trying ot make to compile the Petalinux software image( make in $PETALINUX/software/petalinux-dist) . Refer to the UG977 PetaLinux SDK Getting Started Guide.pdf
However, when it gets to "[INFO ] Expanding stagefs", there is be an error . How can i do it?
My petalinux was installed in Debian-6.0.6-amd64 OS Host (in VirtualBox on my win7).
Thanks in advance!
Here is my PetaLinux compilation progress output:
$PETALINUX/software/petalinux-dist$ make
[INFO ] Saving previous build.log
[INFO ] Building ucfront tool
[INFO ] Building kernel
[INFO ] Building kernel modules
[INFO ] Building include
[INFO ] Building rootfs
[INFO ] Setting up stage config
[INFO ] Setting up romfs config
[INFO ] Updating for microblazeel-v830-bs-cmp-mh-div
[INFO ] Updating package manager
[INFO ] Expanding stagefs
[ERROR] E: Sub-process /home/focs/petalinux-v2013.04-final-full/software/petalinux-dist/tools/packagemanager/bin/dpkg returned an error code (127)
[00:02] \ make[1]: *** [pkg_stagefs] Error 255
make: *** [subdirs] Error 1

I am seeing the same error.
Environment:
Host PC : CentOS-6.5-x86_64
Xilinx Tools: Vivado 2013.3
PetaLinux Release: 2013.10
Page 11 of The Petalinux Installation guide document shows the packages required for Petalinux installation in the 1st column. I have installed all these packages except libstdc++-4.4.6-4.el6.i686. The only version readily available was libstdc++-4.4.7-4.el6.i686.
http://www.xilinx.com/support/documentation/sw_manuals/petalinux2013_10/ug976-petalinux-installation.pdf
sudo yum install dos2unix iproute gawk gcc git gnutls-devel net-tools ncurses-devel tftp-server zlib-devel flex bison libstdc++-devel.i686 glibc.i686 libgcc.i686
Loaded plugins: fastestmirror, refresh-packagekit, security
Loading mirror speeds from cached hostfile
* base: centos.mirror.lstn.net
* extras: mirror.ubiquityservers.com
* updates: centos.gravityfish.com
Setting up Install Process
Package dos2unix-3.1-37.el6.x86_64 already installed and latest version
Package iproute-2.6.32-31.el6.x86_64 already installed and latest version
Package gawk-3.1.7-10.el6.x86_64 already installed and latest version
Package gcc-4.4.7-4.el6.x86_64 already installed and latest version
Package git-1.7.1-3.el6_4.1.x86_64 already installed and latest version
Package gnutls-devel-2.8.5-10.el6_4.2.x86_64 already installed and latest version
Package net-tools-1.60-110.el6_2.x86_64 already installed and latest version
Package ncurses-devel-5.7-3.20090208.el6.x86_64 already installed and latest version
Package tftp-server-0.49-7.el6.x86_64 already installed and latest version
Package zlib-devel-1.2.3-29.el6.x86_64 already installed and latest version
Package flex-2.5.35-8.el6.x86_64 already installed and latest version
Package bison-2.4.1-5.el6.x86_64 already installed and latest version
Package libstdc++-devel-4.4.7-4.el6.i686 already installed and latest version
Package glibc-2.12-1.132.el6.i686 already installed and latest version
Package libgcc-4.4.7-4.el6.i686 already installed and latest version
Nothing to do
When I run petalinux-buiild from the project Xilinx-ZC702-2013.3 directory, I see the same error.
$ cd petalinux-v2013.10-final/
$ source settings.sh
PetaLinux environment set to '/home/logic/petalinux-v2013.10-final'
INFO: Checking free disk space
INFO: Checking installed tools
INFO: Checking installed development libraries
INFO: Checking network and other services
$ cd ../Xilinx-ZC702-2013.3/
$ petalinux-build
INFO: Checking component...
INFO: Generating make files and build linux
INFO: Generating make files for the subcomponents of linux
INFO: Building linux
[INFO ] pre-build linux/rootfs/fwupgrade
[INFO ] pre-build linux/rootfs/peekpoke
[INFO ] pre-build linux/rootfs/uWeb
[INFO ] build linux/kernel
[INFO ] update linux/u-boot source
[INFO ] generate linux/u-boot configuration files
[INFO ] build linux/u-boot
[INFO ] Setting up stage config
[INFO ] Setting up rootfs config
[INFO ] Updating for armv7a-vfp-neon
[INFO ] Updating package manager
[INFO ] Expanding stagefs
[ERROR] E: Sub-process /home/logic/petalinux-v2013.10-final/tools/packagemanager/bin/dpkg returned an error code (127)
[ERROR] make[2]: *** [pkg_stagefs] Error 255
[ERROR] make[1]: *** [sub_build_component_/none/packages-repo/single/plnx-repo] Error 2
ERROR: Failed to build linux

PetaLinux Userspace App - Zynq PL stuck in reset?

Hello. I'm trying to convert our bare-metal application to a PetaLinux userspace application. I seem to be able to mmap some physical addresses to virtual memory and read some pseudo-serial number that we've stored in a register. But I can't seem to read or write any other active registers. It is as if the FPGA fabric is stuck in reset while the PS runs PetaLinux just fine. I'll outline most of my steps in case the error is early in the process.
Our board is very similar to the ZC0702 Eval Board so I use the -s option with the ZC0702 BSP when creating the PetaLinux project.
I can configure, build, and boot the PetaLinux project successfully (using our bitstream with petalinux-boot --jtag --fpga --bitstream <BITSTREAM>).
I can compile and run a test program from the Xilinx SDK that prints our test serial number from a mem-mapped register:
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/mman.h>
#include <fcntl.h>
static const unsigned VX_BASE_ADDR = 0x68A00000; /* base address stores "serial number" */
int main(int argc, char *argv[]) {
/* initialize values */
int fd, value = 0;
unsigned page_addr, page_offset;
unsigned *basePtr, *ledPtr;
unsigned page_size = sysconf(_SC_PAGESIZE);
/* open /dev/mem file */
fd = open ("/dev/mem", O_RDWR | O_SYNC);
if (fd < 1) {
perror(argv[0]);
return (-1);
/* mmap the reg address into memory */
page_addr = (VX_BASE_ADDR & (~(page_size-1)));
page_offset = VX_BASE_ADDR - page_addr;
basePtr = mmap(NULL, page_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, page_addr);
/* read value at address */
value = *((volatile unsigned *)(basePtr + page_offset));
printf("%08x\n",value);
/* release memory */
munmap(basePtr, page_size);
return (0);
Which gets this output:
root@Xilinx-ZC702-2014_4:~# echo $PWD'>'
/home/root>
root@Xilinx-ZC702-2014_4:~#
root@Xilinx-ZC702-2014_4:~# /home/root/vx_test.elf
12345678
root@Xilinx-ZC702-2014_4:~#
root@Xilinx-ZC702-2014_4:~# exit
logout
Looks good - 12345768 is our testing serial number! Everything seems ok at this point...
5. But when I try to read / write additional registers, I don't get anything:
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/mman.h>
#include <fcntl.h>
static const unsigned VX_BASE_ADDR = 0x68A00000;/* base address of the "serial number" */
static const unsigned VX_LED_ADDR = 0x41200000;/* LED control register */
static const unsigned VX_RDOUT_DUR_REG_ADDR = 0x00000015;/* offset from VX_BASE_ADDR */
int main(int argc, char *argv[]) {
/* initialize values */
int fd, value = 0;
unsigned page_addr, page_offset;
unsigned *basePtr, *ledPtr;
unsigned page_size = sysconf(_SC_PAGESIZE);
/* open /dev/mem file */
fd = open ("/dev/mem", O_RDWR | O_SYNC);
if (fd < 1) {
perror(argv[0]);
return (-1);
/* mmap the reg address into memory */
page_addr = (VX_BASE_ADDR & (~(page_size-1)));
page_offset = VX_BASE_ADDR - page_addr;
basePtr = mmap(NULL, page_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, page_addr);
/* read value at address */
value = *((volatile unsigned *)(basePtr + page_offset));
printf("%08x\n",value);
/* write value out to address */
printf("Before Write: %08x\n", *((volatile unsigned *)(basePtr + (VX_RDOUT_DUR_REG_ADDR << 2))));
*((volatile unsigned *)(basePtr + (VX_RDOUT_DUR_REG_ADDR << 2))) = 0xff;
sleep(1);
printf("After Write: %08x\n", *((volatile unsigned *)(basePtr + (VX_RDOUT_DUR_REG_ADDR << 2))));
/* mmap the LED address into memory */
page_addr = (VX_LED_ADDR & (~(page_size-1)));
page_offset = VX_LED_ADDR - page_addr;
ledPtr = mmap(NULL, page_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, page_addr);
/* turn on LEDs */
*((volatile unsigned *)(ledPtr + page_offset)) = 0xff;
/* sleep to confirm LED */
sleep(2);
/* release memory */
munmap(basePtr, page_size);
munmap(ledPtr, page_size);
return (0);
Output:
root@Xilinx-ZC702-2014_4:~# echo $PWD'>'
/home/root>
root@Xilinx-ZC702-2014_4:~#
root@Xilinx-ZC702-2014_4:~# /home/root/vx_test.elf
12345678
Before Write: 00000000
After Write: 00000000
root@Xilinx-ZC702-2014_4:~#
root@Xilinx-ZC702-2014_4:~# exit
logout
(No LEDs have turned on).
6. I created this test application using our system_stub.hdf, and it seems to have mapped everything appropriately:
I'm pretty new to all of this, so it's unclear to me the best way to make sure the userspace application is informed about the hardware.
Am I supposed to initialize the FPGA fabric in some way before trying to access these registers? Am I missing any obvious (or non-obvious) steps?
Any help you can provide would be greatly appreciated.
Thanks,
Greg

Hi,
in the same spirit,
With Board zc702
Petalinux 2015.2,
Create a new project from bsp file ,
petalinux-create -t project -s ./Xilinx-ZC702-v2015.2-final.bsp -n test703
After copy the content of the subfolder 'test703/pre-built/linux/images' on a SD-card,
The system start correctly,
After logon a simple:
poke 0x41200000 0 will hangs the system,
I tried this project after some tests with other board and projects coming from vivado,
It's always the same,
For me the problem comes from the FCLK_CLK0, this signal disappear after the boot,
The system hang because this clock is used by the AXI interfaces.
Before I used petalinux 2014.2, it was ok for this function.
All tests are ok with standalone os.
Best regards.
Gérard.

SDK Help with g

I have a reference design that I have generated and I have exported this to SDK and imported an archived file that I believe contains all of the source files and libraries that I need. I have just started to use SDK and I am unsure of how to generate a bitmap. I could really use a tutorial that goes step by step through the SDK process. I can provide the vivado and SDK files if necessary.
I am using the 2015 version of Vivado and SDK I am also using the KC705 with a FMC board attached.
Thank you for your time and any help that you could provide me.

Hi
Sure. You can check the following tutorial. This goes through the flow in embedded systems.
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug940-vivado-tutorial-embedded-design.pdf
Hope this helps.
Regards
Sikta

BSP gen in Vivado - failing to execute Tcl commands.

Hi All,
Likely a noob question here. Using distro 2014.4. I am trying to run individual tcl commands as per UG1138: Generating basic software platforms, in order to generate a BSP with advance settings.
More specifically, I refer to the Appendix C of the doc: "BSP, DTS and Application Generation in Vivado".
Now, I figured the "Vivado%" prompt in the instructions would require opening Vivado in tcl mode, which I did in a Xilinx SDK shell (getting the same results when starting Vivado 2014.4 Tcl Shell).
So early lines proposed in Appendix C give errors:
Vivado% common::load_features hsi
invalid command name "common::load_features"
Vivado% load_features hsi
ERROR: [Common 17-220] No such feature 'hsi'. Available features are: board ipin
tegrator ipservices labtools simulator updatemem
Vivado%
I feel like I am probably missing something obvious here.
Any help appreciated.
--Martin

Hi stephenm,
in shell open from SDK "Xilinx Tools -> launch shell": C:\apps\Xilinx\SDK\2014.4\bin\hsi.BAT
on windows cmd.exe: which: no hsi in (<whole system path>)
Also this is working after installing 2015.5:
Vivado 2015.5 Tcl Shell
vivado % list_features
board hsi ipintegrator ipservices labtools simulator
In 2014.4, I was not seeing "hsi" listed in the features.
So it seems like it can work as advertise by the doc.
I think I was mislead by the doc (v2015.2) while using 2014.4.
also maybe some bug problems were resolved since then.
Thanks a lot for the help, it's really appreciated!
--Martin

Vivado 2015.1 Bug Report: Adding Required Port without Default Value in Custom Interface Definition

When adding a port using the Custom Interface Definition window and not defining a Default Value, the attached error message appears. Not only are the html tags visible, but this error should not be thrown in the first place if both Master/Slave Presense is set to "required". As it is, a port can only be added if a Default Value is given, but can be removed later from the ports table.

yes,I have successfully install petalinux2015.2,but,the issue still be the same as before,the axi 16550 is not working,when I run echo 123 > /dev/ttyS1,my ttyPS0 stop working and axi com keeping null output...
then,I try petalinux2014.4+petalinux2014.4,the difference is the ttyPS0 still alive but axi-com still null...
I found that pl.dtsi file is quite different between the three mode:
M1,petalinux2014.4+vivado2015.1
M2,petalinux2015.2+vivado2015.1
M3,petalinux2014.4+vivado2014.4
most confuse for me is the interrupt ID,
in vivado I connect the axi intterrupt to ID 62 but I get different auto generate dts file
M1:nothing about interrupt and i add manuually in system-top.file
M2:vivado ID is 61 but dts "interrupts = <0 30 4>"
M3:vivado ID is 62 but dts "interrupts = <0 31 4>"
does petalinux auto detect the vivado interrupt connection and ID and write to dts file right or User have to verify and rewrite in ststem-top.dts?
working hard for the issue and hope for a axi demo including petalinux + vivado ,help please

Compiling AXI DMA linux drivers in SDK.

Hi guys,
I think I'm doing something wrong and It's making me crazy. I've got:
Vivado 2015.2 w/ SDK.
Zynq zc702.
Tested in Linux 14.04 and Windows 7.
And I want to use the axi dma drivers in a Linux application so that I downloaded the axidma_test.c example. At first most of the linux libraries threw an error until I linked somehow the libraries I found in the git repository "linux-xlnx/include".
Then all of the "linux/*.h" libraries are recognized, but a new error appears: fatal error: asm/linkage.h not found. I tried to include this last one but I just made it worse. I cut down the code so that I only have a small snippet, having the same error:
#include <linux/dma-mapping.h>
int main() {
printf("Hello World\n");
return 0;
I'm starting to think that I'm making it more difficult than it should be.
Could anyone give me some advise how to successfully compile that small snippet? I would really appreciate it.
Regards,
Leroy

Hello Leroy,
Hmmm okay I found the one that I was thinking of:
http://forums.xilinx.com/t5/Embedded-Linux/AXI-DMA-with-Zynq-Running-Linux/m-p/523105#M10658
There's a presentation there with some code. About halfway down the pdf is an explanation of the software architecture for the AXI DMA linux driver and an explanation of where you need to add your application-specific layers and an example of doing so.
As far as compiling, you really need two pieces still (bear in mind, I'm a little out of my area of expertise talking about the linux software side, so someone with more knowledge may correct the finer details. This is based on what I've gathered...):
1) Kernel module to interface from the driver to userspace (for simplicity, you might use UIO for this like the second pdf that linnj posted in that link)
2) Some application that runs in userspace that communicates with 1 above.
For 1, you don't use SDK. You build a cross compile environment dependent on your kernel configuration and follow build steps:
http://www.tldp.org/LDP/lkmpg/2.6/html/x181.html
For 2, you'd use SDK as you are to build a Linux 'Application' (the word seems to have the connotation of running in userspace).

PetaLinux vs Vivado SDK?

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