PXI 652x DIO Readback?

I have a PXI 6528 DIO board with TTL output channels that NI claims to have readback capability.  I think I need readback capability to facilitate SE execution steps.  How can readback be accomplished in SE or DAQmx?  A very old LV 6.1 vi example is available here
http://www.ni.com/example/29102/en/
but SE cannot run an old LV 6.1 vi.  Can someone either answer my question or at least convert the LV 6.1 vi example to LV 2010+??
Thanks for any advice

http://forums.ni.com/t5/Version-Conversion/Example​-VI-for-PXI-652x-DIO-from-LV-6-1-to-LV-2010-11-12-​...
You also need to explain where you got the idea that you need read back capability. An SE step will set the logic states. Do you doubt that the write will not work?

Similar Messages

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    Hello dan_f,
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    Hi jtele1,
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    Thanks for the reply Spencer, yes it turns out the same lines were damaged in both instances. Actually the ports CPBA, CPBB, CBPC were damaged both times.
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  • Defekte PXI-6533 DIO-Karte

    Sehr geehrte Damen und Herren,
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    Greetings Michael

    Guten Tag Herr Müller,
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  • PXI-6528 Watchdog Timer parameters

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    Update:
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  • MAX does not detect my PXI-5122 and PXI-6551 cards in a PXI-1045 chassis.

    I have been using a PC with MXI-3 to PXI-1045 chassis to develop LabView TestStand code.  Things are fine on my development PC.  [Software configuration report attached nireport_rich.txt].
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    NI Script Editor 1.1
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    Hello Maggie,
    Appreciate your assistance and reply.
    The pxisys.ini and pxiesys.ini files are modified by me with referring to
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    2)PXI-6 SW spec,
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    The content in pxisys.ini/pxiesys.ini generated by MAX looks like simple. Consequently, I modified and checked it line by line according to actual hardware of PXES-2590+PXIe-3975. Then, MAX just list devices as described in the first post. I tried to find the root cause but in vain.
    Is this minor issue can be related any incorrect tag lines in pxisys.ini or pxiesys.ini I posted?
    Is any suggestion tests I can do to troubleshoot root cause?
    Looking forward your reply.
    Cheers,
    KL Tseng

  • NI PXI 6251 SPI emulation

    Hi,
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    use the right hardware http://sine.ni.com/nips/cds/view/p/lang/en/nid/202368
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  • Pxi-6562 connector

    I am using a PXI-6562 LVDS DIO board. I will manufacture a custom cable to connect to the PXI-6562 LVDS DIO card. Can you give me the part number of the mating connector that attaches to the PXI-6562 DIO?
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    Hi Roger,
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  • [HELP] NI MAX Error and Lockup...

    I have a NI PXIe 1062Q and NI PXIe 8135.  Windows 7 Professional 64-bit installed.
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    CB2-1-PIPE USB controller
    PXI-2503 Switch
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    Christopher Povey
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    Solved!
    Go to Solution.
    Attachments:
    20150203_090112-NIMax-0000134C.log ‏9 KB
    20150203_090112-NIMax-0000134C.log ‏9 KB
    20150203_090112-NIMax-0000134C.zip ‏26 KB

    I worked it out in the end.
    The PXI chassis came pre-installed with a few cards we had ordered. I think NI installed the drivers for these cards (probably later than 2012). I then removed all the NI software from the Control Panel and installed NI Developer Suite 2012. I think the drivers clashed. I did a full system restore from the image on the drive and re-installed NI Developer Suite 2012 and it was fine.
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  • RT Remote Front Panel issues.

    I'll start with my setup:
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    Could you clarify a bit on how the PXI-6528 was acting while you were seeing these problems? Does this card have values display on the Remote Front Panel, and if so were they still updating properly? I believe you were saying that, but I wanted to be sure because that makes a big difference. 
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  • High Impedance Measurement

    Hello,
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    Ernest
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  • How can I communicate PXI-6509 by Static DIO Register-Level Programming?

    - How can I communicate PXI-6509 by Static DIO Register-Level Programming?
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    Hello!
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  • Regarding NI PXI-6602 - How to route PFI_33 to a grounded DIO Line.

    The PXI-6602 card with the TIO chip seems to be very robust on counter and DIO pin assignments and routing, but I have found that counter 1 has a pin (PFI_33 -AUX IN (UP/DOWN) ) that has been troublesome.  I need to either route this pin to another pin such as a DIO pin set as an output and pulled LOW or be able to manipulate the pin to a low state when I setup counter 1.  This is to ensure that noise is kept to a minimum due to the PXI-6602 being cabled to a board with a PLD on it.  Any solutions on how to tie PFI_33 low?
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