Rising edge analysis RS FlipFlop without the Reset

Hello, I am a starter with LabView and am trying to create a rising edge analysis. With the first rising edge of a Boolean Signal (an Input) a variable (and an Output) should be set and the second rising edge should reset this variable. It is like a RS Flip-flop with the second Set Signal as Reset.
By pressing an external pushbutton (my Input) my program should switch on/off my output to control an electrical system.
Maybe anyone can help me, Thank You!
Lars

Here is a simple vi that does the trick. Substitute Boolean with your input and substitute Boolean 2 with your output. You can also make this into a LV2 functional global by moving the Boolean and Boolean 2 out of the loop and making the loop execute only once (replace Stop and Not with False constant). Call the functional global from your main with your input to the connector pane left side and the output comes from the connector pane right side.
- tbob
Inventor of the WORM Global
Attachments:
FlipFlop.vi ‏19 KB

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Hello,
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Therefore the first one have to start on a rising edge of its GATE and stop on the next rising edge. This is not a problem.
But the second one should start on the falling edge (that immediately follows the rising edge) of counter 1 and stop the same time counter 1 will do.
The third one should start after the falling edge of counter 2.
Is this actually possible?
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Regards Thomas

I think I may be a bit confused on exactly what you are trying to accomplish, so if my answer does not
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Hi it's still me with still some troubles
I've generated with my counter0 a square wave of 50 ms pulse width from an internal source but then, I don't know how to specify that this signal will also be the pin gate (ND_PFI_4) of my counter1 which will count the rising edge.
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(ps : can you speak french?)

Rising Edge on AO Start

Hi,
I'm using a PXI 6251 Daq card.
On this one, I'm generate on analog output a finite signal.
I would like to initiate a rising edge on PXIx terminal when the Output analog task is realy run.
In fact i would like to provoq an output trigger when the analog task is start.
Is it possible ?
Thanks for reply.
Regards
=========================
Bonjour,
Je dispose d'une carte PXI 6251
Sur celle-ci je génére un signal Analogique Finit.
Je souhaite provoquer un front montant sur une sortie PFIX quand la tache de génération à démarrer. Puis que cette sortie tombe à 0 quand la tache est stopée....
Est-ce possible ?
Merci pour vos réponses.
Solved!
Go to Solution.

Hello __KB__,
I think you should start from this example : https://decibel.ni.com/content/docs/DOC-5374
Then, you'll have to adapt it in order to define a pattern which generates a high level as soon as the analog task starts and which generates a low level at the end of the finite acquisition.
In order to know which digital line matches with your PFI line, you will have to look at the documentation of the PXI 6251 (http://www.ni.com/pdf/manuals/371291h.pdf, page 14). You can also get the information from MAX.
Regards,
Jérémy C.
National Instruments France
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How can I use the pulse train from a 6602 to trigger an niFGEN and niSCOPE on each rising edge of the pulse train?

Hello,
Here is my application: I need to use a 6602 counter/timer to generate a pulse train of certain frequency and duty cycle. On each rising edge of this pulse train, I need to output an arbitrary waveform on Ch. 0 of an niFGEN (5422) AND acquire data from CH. 0 of an niSCOPE (5124). I also need to synchronize the niFGEN and the niSCOPE to the same clock used for the pulse train (6602/ctr0). This process needs to continue until the user stops the system.
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Questions:
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2.) Once I configure the niFGEN and niSCOPE to be triggered on a digital rising edge, how can I effectively have this happen for every rising edge from the pulse train? In other words, can I just initiate the FGEN outside of the while loop and it will generate a waveform for each rising edge it sees at the source until the while loop is exitted?
3.) Is setting a reference clock for the niFGEN and the niSCOPE the same thing as synchronizing both devices using the same clock that generated the pulse train? It is not clear to me the difference, and why it would necessarily be useful.
Images of my current front panel and block diagram are attached. If you would rather have the actual VI's just let me know. Any help and/or explanation on this is greatly appreciated. Thanks in advance.
Attachments:
Front_Panel_Control.jpg ‏278 KB
Block_Diagram_Control.jpg ‏263 KB

Hello Cgifford,
Welcome to National Instruments Forums.
To output your signal to the PFI lines,
you can use external connectios between OUT0 and PFI lines. You can also use
the backplane to do so by routing into the same RTSI line.
1)
On the SCOPE and FGEN, the name of the
terminals are actually “PXI Trigger Line x/RTSIx” but on the 6602 you might
need to route the signal using the property:
You can also use the DAQmx route signal which perform the same opperation.
2)
This will depend on the frequency of
your pulse train. If this is lower than about 10 ms, then you can probably
place this on a loop and start and stop the acquisition every time. If the
frequency is higher than this, you will have to use:
- Scripting on the FGEN side (read more)
- MultiRecord Fetch (more information in the scope help file
section “Acquisition Functions Reading versus Fetching”).
3)
The short answer is yes. The longer one
might depend on how tight you need the synchronization to be (us, ns, ps). For
very tight synchronization, you should look into here.
Message Edited by Yardov on 06-18-2007 03:14 PM
Gerardo O.
RF Systems Engineering
National Instruments
Attachments:
property.JPG ‏7 KB

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www.ni.com/ask

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Rising edge analysis RS FlipFlop without the Reset

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