RTSI at 80 MHz

Question

Hi
I'm using a NI5640R board. Is it possible to set the RTSI clock at 80 Mhz in the Host vi changing in some way the Configuration timebase vi?
With this vi I can set the RTSI clock at 200 100 50 25 12.5 MHz but 100 is to high for the FPGA vi (the maximun when compiled is 95 MHz)  and 50 is too low for what I need to do. I tried to pipeline the FPGA but there were no significant results.
Thanks in advance for your help.
Emanuele

Answer 1

Hi David
If your code is not in a single cycle times loop, or in the normal while loop, all the code will be clocked at the 20 MHz rate, but that does not mean that the full chain of code will complete in one clock cycle.  In these case most LabVIEW functions will take a number of clock cycles to completes it function.  Then the data is passed onto the next function, and so on until the end of the chain of functions.  Then the loop starts from the beginning again.  A loop will have a loop rate determined by the total length of pipeline delays from each function in the chain.
Here is a link that discusses optimize loops for LV FPGAs.
http://zone.ni.com/devzone/cda/tut/p/id/3749
Jerry