There is an error when compile a FPGA example vi

I just run a simple example vi such as Digital.vi and then found an error "Unable to spawn compiler" in the compile server dialog box. It seems that the FPGA vi can not be compiled.
Could you give me some help?
I am a FPGA freshmen and feel really puzzled.
Thank you!!

Thanks Mike,
I checked the directory according to the steps. Both the path and the configure are correct. Let me express the problem more specifically:
1.Start to compile, the client displays�Successfully started compile�
2.Several seconds later, the server displays�Unable to spawn compiler�
3.Then the client displays"Board clock of 40MHz Met:No(0MHz)"
we checked the xflow.log file and it shows CompileServer got an error when calling Xilinx compile tools.
It seems that the error is caused by inexsitence of file toplevel_gen.prj.
Could you give me more help?Thank you
Best reguards,
Yang Xin

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To compile against to SDK X all I did was:
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HAVE_W32API_H
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Without seeing your code, I can't really help.
If you want help with your code, open a formal support ticket.
From: Adobe Forums <[email protected]<mailto:[email protected]>>
Reply-To: "[email protected]<mailto:[email protected]>" <[email protected]<mailto:[email protected]>>
Date: Tue, 6 Dec 2011 04:09:25 -0800
To: Leonard Rosenthol <[email protected]<mailto:[email protected]>>
Subject: Pragma error when compiling with SDK X
Pragma error when compiling with SDK X
created by magdakuit<http://forums.adobe.com/people/magdakuit> in Acrobat SDK - View the full discussion<http://forums.adobe.com/message/4066378#4066378

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Hello Taylan,
I think the error that you received was due to packaging issues.I placed the
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When you want to access a java class, you can either place the compiled
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"taylan" <[email protected]> wrote in message
news:3d6351b0$[email protected]..
>
I am trying to write a simpe web service in WebLogic Workshop, but havingan error
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Regards,
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package data;
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File Line Message
WebService1.jws 0 Resource found on system classpath: data.UtilClass
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Message Edited by Jerry_L on 03-26-2006 09:28 PM
Message Edited by Jerry_L on 03-26-2006 09:29 PM

Hi Jerry,
I'm just tried to make all these steps by myself (http://zone.ni.com/devzone/cda/tut/p/id/3516). I have generated FIR filter using Xilinx ISE and got *.VHD file which was going to use in HDL Node.
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Actually I need to model FIR filter:
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Filter1.vi ‏16 KB

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I'm trying to get a FFT Core working inside the NI-5640R FPGA. In my latest debugging step, I have received the following error when compiling:
Compiling vhdl file "C:/NIFPGA82/srvrTmp/LOCALH~1/IFBC3E~1/bushold.vhd" in Library work.
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There is an error when compile a FPGA example vi

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