Upgrade to 6.0i from 4.1 causes timing and other changes

Question

I have recently installed 6.0i and want to continue development of the system I started on 4.1. The system is much, much slower on 6.0i and acts differently then on 4.1. A quick(hopefully) overview of the system:
I'm using a PC-DIO-96. The system consists of three main VIs. 'IO test Program.vi' is the user interface and takes care of calling the other VIs and displaying the results. 'init pattern check.vi' is the first part of the test. It will receive a walking 1's pattern from the outputs of the UUT. It compares it with a spreadsheet file and verifies that the outputs of the UUT can be used for the second part of the test. The outputs from the UUT are simulated from a pattern generator within 'init pattern check.vi' and looped from port 3 to port 0 physically, as the UUT is not available yet. The second part of the test is done using 'command mode.vi'. It receives a 8 bit number from the UUT (also generated by the program itself for now) and de-multiplexes it to the 64 output bits which go back to the UUT. The command FF means the test was successful, FE is a failed test. These can be generated as well to simulate.
Okay, now the system ran fine on 4.1. My test pattern could go as fast as 7 ms with a timeout of 500ms in the sub VI, or if I ran it from the top VI, it would need to be 5000ms to be reliable (unless the sub vi window was open in the background, then 500ms worked as well). When I converted them to 6.0i, the warnings I received all concerned data range coercion, which I didn't know I was using, so it shouldn't make a difference. The system now runs extremely slow. Just changing from the front panel to the block diagram takes about 4 seconds, where in 4.1 it didn't take more than .5 sec. When running from the top VI, every second time you run the test, all the bits fail. This shouldn't happen, and I can't figure out why. In the second part of the test, while watching with a logic analyser, bit 64 seems to be stuck on almost all the time.
I'll attempt to attach the files to this message. By the way, this is my first attempt at using LabView for anything, so if it looks like a beginner did it, it's true. Any help or advise you could offer would be greatly appreciated.

Answer 1

Craig Nowak wrote:
>
> I have recently installed 6.0i and want to continue development of the
> system I started on 4.1. The system is much, much slower on 6.0i and
> acts differently then on 4.1. A quick(hopefully) overview of the
> system:
>
> I'm using a PC-DIO-96. The system consists of three main VIs. 'IO test
> Program.vi' is the user interface and takes care of calling the other
> VIs and displaying the results. 'init pattern check.vi' is the first
> part of the test. It will receive a walking 1's pattern from the
> outputs of the UUT. It compares it with a spreadsheet file and
> verifies that the outputs of the UUT can be used for the second part
> of the test. The outputs from the UUT are simulated from a pattern
> generator within 'init pattern c
heck.vi' and looped from port 3 to
> port 0 physically, as the UUT is not available yet. The second part of
> the test is done using 'command mode.vi'. It receives a 8 bit number
> from the UUT (also generated by the program itself for now) and
> de-multiplexes it to the 64 output bits which go back to the UUT. The
> command FF means the test was successful, FE is a failed test. These
> can be generated as well to simulate.
>
> Okay, now the system ran fine on 4.1. My test pattern could go as fast
> as 7 ms with a timeout of 500ms in the sub VI, or if I ran it from the
> top VI, it would need to be 5000ms to be reliable (unless the sub vi
> window was open in the background, then 500ms worked as well). When I
> converted them to 6.0i, the warnings I received all concerned data
> range coercion, which I didn't know I was using, so it shouldn't make
> a difference. The system now runs extremely slow. Just changing from
> the front panel to the block diagram takes about 4 seconds, where
in
> 4.1 it didn't take more than .5 sec.
This issue sounds like the PC is busy. Make sure that each loop has a
delay in it. Once that is fixed, other parts may work better.
Mark