USRP Frequency Translating FIR Filter

Hi,
I would like to use the USRP as a Software Defined Radio where I can sample a wide spectrum (like 20MHz) and then chose to demodulate a small part of the received spectrum. An example is to sample the whole FM radio band from 88MHz to 108MHz and then from these data FM demodulate 200kHz from a station on 103.9MHz or any other selected signal.
With GNU radio I believe this can be performed by a function called Frequency Xlating FIR Filter which can transform the zero frequency of the IQ data, add a FIR filter and then decimate the data. With LabView I have tried several filters, decimations and transformations but I never end up getting a good output.
Can anyone guide me in the right way on how I can do this?
With regards,
-Sigurd A.

Hi,
I forgot to update this post. I did not find any VI which did this but after some studying and trials I found something that seems to work OK for me. See attached picture.
The clue was to multiply the IQ data with a sinus signal with frequency equal to the frequency shift, and with same sample rate and number of samples as the IQ signal.
Then the signals can be decimated to the wanted bandwidth.
With regards,
Sigurd A.
Attachments:
image.jpg ‏176 KB

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Hello again:
Jerry:
1. I referred to the Event structure, but in the HOST, but now, with your commentary and Philippe's explanation i've undestood better the concept.
2. Regarding the filtering, I read the datasheet of the AD6654 (DAC from "Analog Devices" which is part of the n5640r) and in pages 36 and 37, it explains with an example, the possibility of designing a Bandpass CIC Filter by changing the interpolation (or decimation) factor of the DUC (or DDC). The filter can't be fully customized (the rejection and passband are limited to an "Alias rejection Table" in page 36), but it could fit the application to filter certain frequencies.
I also tryed what you guys suggested, meaning: I designed a simple digital bandpass butterworth IIR filter in the FPGA target inside a 3rd SCTL with a faster clock (i.e. "Top level timing source") and using a 2nd Local FIFO. The filter was done with FPGA discrete delays (z^-n) departing from a "differences equation" [y(n) = x(n-1)+x(n)+0.9996858*y(n-1)]. But I have problems with the 0.99... constant which is always rounded to 1 (check the pic). I changed the variable's type and digits of precision, but it still rounds up to 1 Any suggestions?
3. I was thinking as well of shifting the phase (as Jerry said) by configurating the NCO in the DAC. Again, more information is given in AD6654's datasheet (page 35). I will quote the info:
"The phase offset register can be written with a value that is added as an offset to the phase accumulator of the NCO. This 16 bit register is interpreted as 16-bit unregistered integer. A 0x0000 in this register corresponds to a 0 radian offset and a 0xFFF corresponds to an offset of 2pi*(1 - 1/2^16) radians. This register allows multiple NCOs (multiple channels) to be sinchronized to produce complex sinusoids with a known steady phase difference:"
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Thanx in advance for your replies
'till the next post...Antonio
Attachments:
Digital IIR.JPG ‏122 KB

Design a Filter using the Digital FIR Filter.vi

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Hi,
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http://zone.ni.com/devzone/cda/tut/p/id/4759
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PHPATEL.

Hi
I think you posted this to the wrong NI Message board. This is meant for help with the NI PCI-5640R IF Tranceiver.
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Attachments:
Receiver Converter Software.zip ‏938 KB

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Hi
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Presently the need is to design a filter with folllowing characteristics:
1. Phase linearity to be maintained in the pass band.
2. sharp cut off freq band (can be the best possible to optimize speed of computation).
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5. High sampling rate is necessary to maintain the shape of the sign wave since we are more concerned with the phase of the input signal.
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thanks and regards,
sunil
Apna Technologies and Solutions
Bangalore,
Karnataka,
India
Attachments:
snap of FIR narrow LPF.JPG ‏63 KB

Hi,
Thanks for the reply.
The vi is designed but we are having an issue of speed of processing.
This filter takes a long time to process.
We are looking for the following:
Since our signal can range from 0.1Hz to 5Hz our sampling freq needs to be higher, about 8000 samples/s, this is necessary since the shape needs to be maintained for accurate phase measurements (the signal is always sinewave and with noise on it).However you may suggest this sampling rate based on your experience.
Since the phase in the pass band needs to be linear we have to select FIR and since the filter roll off needed is very sharp as provided in the attachment, the resulting design has a large number of taps(coefficients), this makes the processing slow.
--What would be the appropriate sampling frequency for such a filter design.
--Is it that such filters are slow, if so how can they be put in the front end filtering of signals acquired from a daq (PCI-6229)analog channel in a continuous acquisition mode.
we would be thankful for a quick response.
PLS refer to the attachment for filter characteristics.
thanks & regards,
sunil
Apna Technologies and Solutions
Bangalore,
Karnataka,
India

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I can decimate the signal with the coefficient 2, or I can also use the
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Hello,
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by!
Yann Falevoz
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Solved!
Go to Solution.

Thank you guys! I found out what I wanted. But thanks for guiding me.
I'll post the answer so that others can use it
First I found out the transfer function ( from the filter coefficients) of the filter by using:
Digital Filter Design toolkit => Utilities => From TF ( DFD Build Filter from Transfer Function.vi)
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I got the required frequency response .
@Sd.Kfz.10 I coudn't use the FIR filter and IIR filter where coefficients are given as inputs (in signal processing toolkit) because I wanted the response of the filter alone. These FIR and IIR filter requires the input signal array.
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USRP Frequency Translating FIR Filter

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