FIR Maximum Frequency

Question

Hi,
I try to design FIR filters with 501 coefficients (single symmetric coefficient set) an with max frequency > 650 MHz.
Guess it should work because DSP48E1 max frequency is 740 MHz for 7-series -3 devices.
Actually, it works fine if the number of DSP48E1 is very low, but max frequency decreases drastically as the number of DSP48E1 increases.
Timing analysis gives the following results Constraint period is set to 1.425ns (700 MHz) :
For a 13 coefficients FIR filter, timings are correct :
Setup slack : 0.088 ns (748 MHz)
Min Pulse width : 0.075 (741 MHz)
For a 61 coefficients FIR filter, timings are :
Setup slack : -0.142 ns (638 MHz)
Min Pulse width : 0.075 (741 MHz)
Worst setup timing is between DSP48_X0Y19 PCOUT and DSP48_X0Y20 PCIN, that is at a clock region boundary.
Setup slack increases to 0.022ns, which is fine, if the FIR DSP slice column option is set to 20, 11 instead of the default value 31. Doing that, all DSP48 are in the clock region X0Y0.
Unfortunately, that strategy doesn't work for 501 coefficients!
Is there a way to improve the timing between PCOUT and PCIN at clock region boundaries?

Answer 1

You can try to use Xilinx FIR compiler IP