What are the 3-bit field choices for Hw_Arm_Sel in PCI-6601

Question

Hi,
I am programming our own driver to operate the PCI-6601. For our application we need hardware arm option. I know it is possible to use 2 counters for that, but NI-TIO should support also hw_arm. Although it is not explained in the registry document at all, after some tedious check in the DDK examples I found that this bits are located in the Gi counting mode register. I know the position of the HW_enable as well as the position of the 3 bits for pin sellect options. What I do not know is What are the 3-bit field choices for Hw_Arm_Sel . I contacted NI support but got no support. How can NI sell boards and when a customer who is not using LAbview or Measurement Studio or DDK, but is implementing his own driver is then so arrogantly turned down from NI? Also, how can NI publish just part of the registers the board support, and when a customer contacs and asks for some registers get not at all support? I can not foretell the missing registers, and it is pretty unprofessional to document just partly the registers of 660x devices. And on request you got nothing.
I hope someone from the community know about this Hw_Arm_Sel 3 pin options. Otherwise, there is just an option of error and trial. Or simply throw the board in the garbage.
Dr. Kirco Arsov
Solved!
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Answer 1

Hi Kirco,
I have some more information for you :-)
I haven't been able to speak to the developer who is the most familiar with TIO programming since he's out of the office, but I have come across his notes from when he was writing support for the DAQmx driver.
As I described earlier, the HW_Arm_Sel bits don't select a connector I/O pin, but an internal trigger signal. There are seven internal trigger lines, and the HW_Arm_Sel bits map directly to the internal trigger signal: 0b000 - 0b111 map to 0d0 - 0d7. In order to route an I/O pin to an internal trigger, you must also write to a few more registers.
From what I've read, there are two more register families that need to be programmed: TG_x_LevelEdgeReg and TG_x_CombinationReg, where x is the internal trigger number. In your case, you only need one pin from the I/O connector to be your arm start trigger, so TG_0_LevelEdgeReg and TB_0_CombinationReg will suffice for your application.
TB_0_LevelEdgeReg :: Offset 0x660
TG_0_LevelEdgeReg is only 8 bits wide, and maps as follows:
7..6: EdgeMode
5..0: LESel
LESel selects the I/O connector pin to use as the source for the internal trigger signal. 0d0 - 0d39 will select the I/O pin of the same number. NB: behavior for TG_x_LevelEdgeReg is more limited for triggers 1-7, and only a small subset of the I/O pins can be selected for those trigger signals. Trigger 0 can use any I/O pin. Setting these bits to 0d63 forces the trigger source low, and can be used as a way to 'unroute' it when you're finished with your program.
EdgeMode determines whether the TIO will detect an edge of the incoming signal, or just pass the signal level straight through. When detecting edges, it will latch the signal and generate a single TIMEBASE3 pulse instead. 0b00 sets level mode; 0b01 sets rising edge; 0b10 sets falling edge; 0b11 sets either edge.
TG_0_CombinationReg :: Offset 0x6A0
TG_0_CombinationReg is 32 bits wide, and has three fields of interest:
19..16: CombFunction
5..4: CombTypeB
1..0: CombTypeA
CombTypeA controls which trigger subsystem to use as the source for the trigger signal. Since you're coming from an I/O pin and using the edge/level subsystem, you must set these bits to 0b01.
CombTypeB is similar to CombTypeA, and although you won't be using trigger B, set it to 0b01 to be safe.
CombFunction performs a simple logic function on A and B. Since you're only using a single I/O connector, you only need the A output, so set these bits to 0b1100.
All of the other bits should be set to 0b0.
Unfortunately, I'm unable to test these statements since my test machine is currently being used for another research project. Please let me know what happens if you decide to test.
Joe Friedchicken
NI VirtualBench Application Software
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