Why do I get such low bandwidth using buffered encoder reads?

Question

I have a PXI system with 10 6115 A/D boards and a 6608 timing board. I can do a simultaneous buffered AI at 5 MHz across all 40 channels of the 6115's.
However, I can only do a single buffered encoder read at about 100 kHz.
Why such a huge difference in bandwidth?

Answer 1

I think the difference in bandwidth here is really due to size of the FIFO's present on each device. The 6115 has either a 16 or 32 Mega-Sample FIFO for analog input. If one of the 6115's isn't granted usage of the bus for a "large" amount of time, it can absorb this by backlogging the data into its FIFO until it is granted the bus, at which time the DMA controller will move the data to host memory before the FIFO overflows. The same is not true of the counters on the 6608. Each counter on the 6608 has an effective FIFO size of 2 Samples. This means at high sampling rates, the 6608 cannot withstand "large" amounts of time without being granted usage of the bus. How fast you can go before the counter FIFO overflows is going to be system dependent, but 200 KHz is in line with results I have observed. If you need to go faster, you can use two counter measurement methods, but you will sacrifice accuracy for speed. For example, by dividing down your input signal by 4, you will be able to go 4 times as fast, but your accuracy will also decrease by a factor of 4. You'll have to weigh the requirements of your application to determine if this type of trade off is acceptable.