XST producing seemingly random results

Question

Hi,
I have a circuit which I am synthesizing in XST and eventually building into a bit file. The problem is that some times the bitfile doesn't work and simply regenerating the netlist with a change in some parameter (say Safe Implementation) and no changes in verilog generates a bitfile that works. Thus every change to the verilog I make is resulting in this frustrating cycle ot synthesize-test-synthesize again-test again.
I brought out some of the internal signals of the design out and the times when the design fails, the condition that it fails on is impossible with the correct interpretation of my verilog (1 signal is an input two 2 modules. One of the modules waits infinitely for that signal to become valid while the other proceeds). 
Also, post synthesis simulation works in both cases. I am pretty much at my wits end here.
Any help would be greatly appreciated.
EDITL I'm using 12.4
Thanks!

Answer 1

Bad results from synthesis are rare in my experience. Unless you are comparing specific netlist-level logic which is seen to be incorrect in FPGA Editor (I've even seen a false positive here from the Technology Viewer schematic view), it is much more likely that another problem exists, which might include:
-unconstrained timing paths
-incorrect timing constraint (e.g. period of 10ns instead of 8ns)
-part below correct voltage, too much voltage ripple, too high of Tj for device), etc.
-incorrect I/O standard, wrong Vcco, etc.
-unconstrained I/O placement (<100% LOCed IOBs in map report) and actual placement varies between runs. Sometimes where you want it to really be. Sometimes not
-flip flops not being packed into IOB and FPGA-level set-up/hold time and/or clock-to-out varies between runs based on actual placement
-difference in BUFG/DCM placement impacting external effective FPGA timing
-running component outside of its spec (e.g. not following DCM high/low input/output rates for respective DLL & DFS range)
-targetting wrong speed grade part (e.g. -2 instead of -1)
-inproperly synchonized inputs to state machine
-clock issue, including improperly handling clock domain interfacing
-reset issue (e.g. asynchronous reset causing issue with one-hot state machine initialization)
-uncovered logic condition that fails to show up in simulation
-using a different clock and/or frequency that you think you are
-other board level issue other difficult to troubleshoot issue: simultaneous switching output, crosstalk, too much ripple on adjacent memory interface termination voltage, etc.
Yes, I've seen all of these...
Other useful info:
http://www.xilinx.com/products/quality/fpga_best_practices.htm (FPGA Design Best Practices)
bt