Sytem Generator generated IP simulation mismatch

Hi,
I am using Vivado 2014.2 & SystemGenerator 2014.2
To demonstrate the problem I have made a simple register using System Generator MCode block. Converted that in to an IP to be used in Vivado IP Integrator.
I insert my simple register IP, generate an HDL wrapper and with a testbench I simulate it.
The problem is that there is a mismatch between the Behavioral simulation and the post-synthesis. The behavioral simulation result shows that no register is infered where as post-synthesis simulation seems correct. Results are shown below.
Could this be a bug? or am I missing something.
I am also attaching files needed to reproduce the problem.
Regards

yes post synthesis simulation seems correct. Can you generate the RTL and see if it infer reg correctly

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    oracle.dms.context.internal.jse.JSEContextManager(JSEContextManager.java:63):getContext
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    Binary Data Not Displayed
    Message Parameters:
    id = 1362724662068-644430531
    Header Parameters:
    filename=MyCompany_ADTA03_2.3.1_1.txt
    filesize=450
    file_ext=txt
    fullpath=C:\tmp\blite\test\in\MyCompany_ADTA03_2.3.1_1.txt
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    Associated Endpoint:
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    Message Body :
    Binary Data Not Displayed
    Message Parameters:
    id = 1362724662068-644430531
    Header Parameters:
    filename=MyCompany_ADTA03_2.3.1_1.txt
    filesize=450
    file_ext=txt
    fullpath=C:\tmp\blite\test\in\MyCompany_ADTA03_2.3.1_1.txt
    timestamp=2011-06-24T16:16:42.000+05:30
    Associated Endpoint:
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    null
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    ----------------------------------------------------------------------------------------------

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