AXI memory mapped to PCI Express BAR0 size in Root Complex

Question

I am using AXI memory mapped to PCI express (2.5) IP as a Root complex in my design.
I have selected the maximum BAR0 Size as 2 GB under PCIE:BARS and AXI-PCIe BAR translation as 0x00000000.
I want to access a memory in the host side of the Root complex using an endpoint.
When I tried to access the address more than 0x7FFF_FFFF from the endpoint in my testbench, the transaction is getting lost in the PCIe section of the IP. I don't see any AXI transaction in the output of the AXI.
Any transaction from the endpoint to address less than 0x80000000 goes through.
Is this a limitation in the IP?
What is the solution if we want to access 4GB of memory from the endpoint thorugh the Root complex?

Answer 1

Hi Suresh,
This is a known issue with the core.  This is targeted for fix in the next Vivado release, where you will either have the option of selecting a 4G BAR for the RP, or masking out the RP BAR altogether, which will allow the full 4G memory space to accept requests from the downstream devices.