Bitstream Generation Error

Hi,
While generating the bitstream for my module, I get the following errors. I have used the Constraints Wizard to generate the constraints. Why cannot I generate the bitstream file?
Route Design
[Route 35-11] Unplaced Non Vcc/Gnd instance 'bufg_clk_freerun_inst' found.
[Route 35-66] The design is not fully placed. There are 1 unplaced non Vcc/Gnd instances. The router will ignore these and continue.
[Route 35-13] Driverless net found. Design will not pass DRC check. Router will skip net hb_gtwiz_reset_clk_freerun_buf_int
Write Bitstream
[DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 5 out of 7 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: hb_gtwiz_reset_clk_freerun_in, hb_gtwiz_reset_all_in, link_down_latched_reset_in, link_status_out, link_down_latched_out.
[DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 79 net(s) are partially routed. The problem bus(es) and/or net(s) are gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].wr_probe_out[1]_i_2_n_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].wr_probe_out[1]_i_4_n_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].wr_probe_out[1]_i_5_n_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].wr_probe_out[2]_i_2_n_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].wr_probe_out[2]_i_5_n_0, hb_gtwiz_reset_clk_freerun_in_IBUF_inst/O, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/Probe_out_reg[0]_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/Probe_out_reg[0]_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/Probe_out_reg[0]_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_IN_INST/addr_count[2:0], gtwizard_ultrascale_0_vio_0_inst/inst/DECODER_INST/clear, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg_n_0_[0], gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_IN_INST/data_int_sync1[15:0], gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_IN_INST/data_int_sync2[15:0], gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_IN_INST/dn_activity_reg_n_0_[0] (the first 15 of 24 listed).
[DRC 23-20] Rule violation (RTSTAT-5) Partial antenna - 34 net(s) have a partial antenna. The problem bus(es) and/or net(s) are gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].wr_probe_out[1]_i_2_n_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].wr_probe_out[1]_i_4_n_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].wr_probe_out[1]_i_5_n_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].wr_probe_out[2]_i_2_n_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].wr_probe_out[2]_i_5_n_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/Probe_out_reg[0]_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/Probe_out_reg[0]_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/Probe_out_reg[0]_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_IN_INST/addr_count[2:0], gtwizard_ultrascale_0_vio_0_inst/inst/DECODER_INST/clear, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg_n_0_[0], gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_IN_INST/data_int_sync1[15:0], gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_IN_INST/data_int_sync2[15:0], gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_IN_INST/dn_activity_reg_n_0_[0], gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_IN_INST/dn_activity_reg_n_0_[15] (the first 15 of 24 listed).
[DRC 23-20] Rule violation (RTSTAT-6) Partial conflict - 42 net(s) have a partial conflict. The problem bus(es) and/or net(s) are gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].wr_probe_out[1]_i_2_n_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].wr_probe_out[1]_i_4_n_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].wr_probe_out[1]_i_5_n_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].wr_probe_out[2]_i_2_n_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].wr_probe_out[2]_i_5_n_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/Probe_out_reg[0]_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/Probe_out_reg[0]_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/Probe_out_reg[0]_0, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_IN_INST/addr_count[2:0], gtwizard_ultrascale_0_vio_0_inst/inst/DECODER_INST/clear, gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg_n_0_[0], gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_IN_INST/data_int_sync1[15:0], gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_IN_INST/data_int_sync2[15:0], gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_IN_INST/dn_activity_reg_n_0_[0], gtwizard_ultrascale_0_vio_0_inst/inst/PROBE_IN_INST/dn_activity_reg_n_0_[15] (the first 15 of 25 listed).
[DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 7 out of 7 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: mgtrefclk0_x0y0_p, mgtrefclk0_x0y0_n, hb_gtwiz_reset_clk_freerun_in, hb_gtwiz_reset_all_in, link_down_latched_reset_in, link_status_out, link_down_latched_out.
[DRC 23-20] Rule violation (UNPL-1) Unplaced Cell - bufg_clk_freerun_inst is not placed. Every cell must be placed in order to generate a valid bitstream. Please run tcl command place_design
[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
Thanks,
Ritwik

Hi,
I was trying to run the IP design example for the GTH transceiver core and while running it, it gave me the same errors. How do I deal with the problem ports. I cannot understand where should I connect these ports and how in order to run the bitstream file.
5 out of 7 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: hb_gtwiz_reset_clk_freerun_in, hb_gtwiz_reset_all_in, link_down_latched_reset_in, link_status_out, link_down_latched_out.
7 out of 7 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: mgtrefclk0_x0y0_p, mgtrefclk0_x0y0_n, hb_gtwiz_reset_clk_freerun_in, hb_gtwiz_reset_all_in, link_down_latched_reset_in, link_status_out, link_down_latched_out.

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Building a multi-folio in InDesign 6 Folio Builder V30. Received "Content generation error. Failed to Export the PDF file" on several of the spreads. I have tried reducing the original pdf files sizes, but that did not help.
Any suggestions on other possible causes or way to fix.?
thanks
Christopher Huber
MMN

I'm very new to DPS so I hope the following description makes some kind of sense.
My magazine is in the process of doing trial runs for an iPad edition. I'm setting some templates up for us to work off so the process from magazine to iPad will run a lot smoother month to month.
So far I've set up some dummy stock pages in an InDesign CS6 document, currently 15 pages long.
All images are linked and all fonts have paragraph styles applied to them.
I'm at the stage I want to check the document on my iPad to test run font sizes and their legibility.
We have successfully been able to export the document as a jpg file but we really need the PDF format. When attempting this we get the above message.
Sonia.

Code generation error when implementing an accumalator

Hi everyone,
I am implementing an accumalator which implements X = X + Y where X and Y are memories of length say 5. Initially I write 5 values into X and Y using a for loop. Then I perform the addition inside a single cycle timed loop and store the results in a temporary buffer(another memory) again of length 5. In another single cycle timed loop, I copy the data from the temporary buffer to memory X.
I changed the arbitration option to never arbitrate for X, but I get a code generation error because of arbitration. Could anybody please tell how to solve this problem.
Regards,
Prashant
Solved!
Go to Solution.

Hi NitzZ
I figured out a way to solve the problem. I chose the "Never Arbitrate" option for all memories and replaced the for loop with a timed loop. Now there are no errors.
Thanks,
Prashant

Code Generation Error - SUP 2.2 / SUW 2.2

Hi,
I have formatted my laptop PC and re-installed Sybase Unwired Workspace 2.2. After the installation I get Code Generation Error message:
Before Code Generarion attemp the Java Build Path / Source tab is empty and after the Code Generation the error specified above is generated and the following path is added to the Java Build Path / Source tab:
XXX/Generated Code/src (missing)
I cannot resolve the problem. Does anybody has idea about the problem?
thanks,

Hi,
1. I created a new model having only one MBO and generated code successfuly.
2. The result is the same after deletion of "Generated Code" and creating new folder
3. The result is the same after generation code to another folder.
nothing has changed but I discovered additional information in the "workspace\.metadata\.log" file:
com.sybase.uep.tooling.codegeneration.coordinator.CoordinatorException: Member not found: inverseClass on object com.sybase.afx.compiler.AttributeDef@2a3881
at com.sybase.uep.tooling.codegeneration.coordinator.impl.ClientObjectAPICoordinator.sendRequest(ClientObjectAPICoordinator.java:115)
at com.sybase.uep.tooling.codegeneration.ui.CodeGenerationJob.sendRequest(CodeGenerationJob.java:200)
at com.sybase.uep.tooling.codegeneration.ui.CodeGenerationJob.processTasks(CodeGenerationJob.java:172)
at com.sybase.uep.tooling.codegeneration.ui.CodeGenerationJob.runInWorkspace(CodeGenerationJob.java:123)
at org.eclipse.core.internal.resources.InternalWorkspaceJob.run(InternalWorkspaceJob.java:38)
at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
Caused by: com.sybase.uep.tooling.codegeneration.clientobjectapi.ClientObjectAPIException: Member not found: inverseClass on object com.sybase.afx.compiler.AttributeDef@2a3881
at com.sybase.uep.tooling.codegeneration.coordinator.CoordinatorException.<init>(CoordinatorException.java:27)
... 6 more
Caused by: com.sybase.modeling.templatej.runtime.adapter.impl.NoSuchMemberException: Member not found: inverseClass on object com.sybase.afx.compiler.AttributeDef@2a3881
at com.sybase.uep.tooling.codegeneration.CodeGenerationException.<init>(CodeGenerationException.java:26)
at com.sybase.uep.tooling.codegeneration.clientobjectapi.ClientObjectAPIException.<init>(ClientObjectAPIException.java:27)
at com.sybase.uep.tooling.codegeneration.clientobjectapi.impl.ClientObjectAPIDelegator.generate(ClientObjectAPIDelegator.java:155)
at com.sybase.uep.tooling.codegeneration.coordinator.impl.ClientObjectAPICoordinator.sendRequest(ClientObjectAPICoordinator.java:86)
... 5 more

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