Counter issue error 200305

Question

Okay here it goes,
I am trying to output the following variable finite pulse trains out of a counter on my 6071E.  First the period must be able to go up to 100ms and second, I must be able to output this pulse train a fixed number of pulses up to 1500 but doing this gives me a error 200305. 
I assume this is due to the overflow of the counter.  I know that because I am using a 6071E DAQ board, which I believe has 24 bit counters, therefore, I can only do 0.8388608 Seconds of output (2^24 Counter/ 20 MHz Clock Rate) without changing my clock source.  So I tried changing my clock signal to the 100 kHz sample clock, which I believe could give me about 167 Seconds (2^24 Counter/ 100 kHz Clock Rate) perfect. 
Okay that leads me to my problem.  Now I have the time limits I need but I don't have the precision.  By decreasing the clock rate I increased my error.  For instance if I have 1500 pulses at 10 ms PulseWidth by 100ms Period I could have an extra 15ms (or actually like 14.99 ms) of Pulse width in there 1.5% (unacceptable) rather than the 75us (or .0075%) with the 20MHz clock (acceptable).  I can live with anything under 0.1% how would I achieve this?  Can I set the counter that generates the Pulse Width and Period to the 20 MHz clock source and the one that controls the Gating to the 100 kHz clock source?  That way I could have the Pulsing error or .0075% and just .002% Gating error that would give me .0095%.  Is this correct?  Do you have any ideas how I can accomplish this? 
Thanks,
Chris

Answer 1

Hi Chris,
I think I’m
a little bit confused by your request, “it would be nice to know how to change the gating and the pulse
train counters independently”, when you refer to
change the gating and the pulse train I guess you mean to change the signal
that is going to drive the GATE and the SOURCE, Am I assuming it right?  If I’m not mistaken you question is driven by
this previous question: “Can I set the
counter that generates the Pulse Width and Period to the 20 MHz clock source
and the one that controls the Gating to the 100 kHz clock source?” If you may explain this a little bit more, please.
If that is
your case you can’t the gate input of the counter is determined by the type of measurement
applications and is controlled by the driver. So pulse generation operates on
the principle of TC every time the terminal count is reached the output of the
counter toggles. Using the gate for a Finite pulse generation will only make
change the number of pulses generated. Generating a Pulse Train
with a Counter.
I hope it
helps
Jaime Hoffiz
National Instruments
Product Expert
Digital Multimeters and LCR Meters