Counter that triggers off the rising and falling clock edges?

Question

I've got an interesting problem of a device that flips its state between high/low everytime an event happens (so two events make one complete cycle).  I'd like to clock an E series synchronously with it, but looking at the documentation I can't see anyway to tell a PFI input or counter to generate a new clock cycle on both the rising and falling edge.  Instead, it just generates a new cycle at half the actual event rate.  
I realize I could generate a new clock at approximately the same frequency using the internal timebase, but unfortunately any jitter between the two clocks must be very, very small (<5 ns) for my application to work and the internal time base doesn't have great resolution.  
Is there some obvious solution I'm missing ?

Answer 1

Nope, E Series can't do this.
Many newer DAQ cards support a feature called "change detection" for digital I/O timing that could be used to generate a sample clock every rising and falling edge of your external signal (you could then export this sample clock or use it for another task).  
You should probably elaborate on exactly what you mean when you say <5 ns jitter though, because this timing requirement is probably going to rule out using these devices anyway.
Best Regards,
John Passiak