CPU Optimization on RT Target

Question

Hello all,
I am working on an issue an would really appreciate some help.
I am using an sbRIO 9612 for a sort of data acquisition procees. I am acuiring  data on the sbRIO and transferring it via network to the host where it is displayed, etc...
My objective is to try to minimize the CPU utilization time on the sbRIO. For this reason I am using a producer consumer architecture where the producer acquires data and buffers it into a queue (or a single process shared variable with FIFO enabled)  at a rate of 1 loop/ms and the consumer is responsible for sending data to the host.
What I was able to achieve is the following:
1. Instead of sending data one item at a time, I used the consumer loop to build an 50 element array of the data and send it every 50 ms to release the CPU for some time. This enhanced the performance by about 15%
2. I also replaced using the shared variables in sending the data to the host by using Network streaming which also reduced CPU usage by 10%.
3. Using Queues instead of the single process shared variables to send data from producer to consumer didn't seem to affect the CPU usage.
I want to know if anybody has other ideas that allow me to further decrease the CPU usage by proposing different approaches, architectures, functions.... anything that might help me have a starting point to think of,
Thank you
Best Regards

Answer 1

I would tweak the size of the "clumps" of data you are sending between your loops and through the Ethernet port to see what is most efficient.  Keep in mind that you are handing data through 3 FIFOs:
1) FPGA to RT - you can change the value of the FPGA Interface.FIFO Read method.  You need to ensure that you are reading often enough to not overflow the buffer, but generally a larger read size at a given thoughput will use less CPU than multiple smaller reads.
2) Producer to Consumer - The Queue/RT FIFO/Shared Variables used to pass data from producer to consumer
3) RT to Host PC (Ethernet, Network Streaming) - most networks max out their throughput and are most efficient near their MTU packet size.  
I have a hypothesis that making the size of the data packet passed from all 3 FIFOs the same size (or a multiple of a common minimum denominator) will help boost performance because you'll be able to pass data around in a manageable chunk rather than breaking it up and reassembling it at each touch point.  By that logic, it would make sense to pick a packet size that is near the MTU size for the Ethernet network, and back propagate that all the way to the RT read from the FPGA.
Hope this helps, and the disclaimer: these are suggestions for things I would try if I were in your shoes, not things I can guarantee will give the ultimate performance boost you may be looking for.  I think your overall architecture is sound, but depending on how complex and sustainable you intend this application to be, you may have a look at a couple resources I found on ni.com, including:
Reference Example for Streaming Data from FPGA to cRIO to Windows (a little older, written in 8.5, so it may not be using some of the new features you've taken advantage of)
Using NI CompactRIO and LabVIEW for Online Signal Processing and Data Recording (intended for inline analysis, but also includes streaming features - takes advantage of the CompactRIO Waveform Reference Library for FPGA to RT streaming - if doing data conversion, fixed to floating point, this example also includes FPGA based IP for conversion that will max your throughput)
Cheers,
Spex
National Instruments
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