CRIO rt timed loop w/ external clock trigger???

I have a feedback control system using a cRIO-9022 and an NI-9401 digital I/O module (among others). I want to use a timed-loop in my RT code to have the execution priority I require. I need to run the timed-loop from an external clock on the NI-9401 input pin. How can this be done?
Thanks,

Hi WhyNot,
Can you elaborate on whether you are using your cRIO's Scan Interface or FPGA Interface to communicate with your 9401? This will make a large difference on your ability to time Real-Time execution with edges coming into your 9401. If you are using the FPGA interface, you may either consider implementing timed loops directly on your FPGA (if the code is not too large), or using a FIFO read from your 9401 on your controller to programmatically gate the execution of your loops. The latter option will not technically be hardware timed but may achieve jitter rates on an order of magnitude of 10s-100s of microseconds depending on your code complexity. If you are using Scan Mode, you may still programmatically gate loop execution based on 9401 inputs but latency will be significant (several milliseconds).
Regards,
Chris E.
Applications Engineer
National Instruments
http://www.ni.com/support

Similar Messages

Why does a CRIO-9004 only provide a timed loop of 1kHz (clock) and not 1MHz?

I essentially have a compact CRIO-9004 and require a PID loop with update rates around 4-5 kHz. Additionally, I was hoping to use multiple 'timed loops' in the program in order to synchronize certain events. During this coding, the timed while loop will not work with a 1MHz clock rate and I am stuck with a clock rate of 1kHz instead. NI claims that PID loops in conjunction with the CRIO may have up date rates as high as 200 ksps. However, it appears that by employing the 1kHz clock that I can only obtain 1 ksps.
What are my options?
Thanks,
Shane

John-
The 9215 has a conversion time of 4.4us when scanning 1 channel (see page 14 of the 9215 operating manual). This equates to a little over 227KS/s. The 100KHz value is if you are reading from all 4 channels.
Link to operating manual:
http://digital.ni.com/manuals.nsf/websearch/5F2E9640C1CFE645862573AF007ABAD9
Dustin
Message Edited by Support on 10-16-2009 09:16 AM

Using NI-9411 in a timed loop clock less than 40Mhz...

Hi,
I'm using a cRIO for motion control. I have a counter that I modified a little bit (from the softmotion examples) and once compiled (unfortunately after 1 hour ...), I have an error saying that I couldn't acheive the desired timed loop clock of 40.4 MHz... the clock rate able to acheived was 40.16 MHz (really near)...
So I had a derived clock of 38.75MHz but this time, before compiling, i have an error saying that theses inputs can't not work at with this time loop clock...
The timed loop counter for this encoder only have to be more than 8000 Hz (1rev/s with 8000 pulses/revolution)
What can I do?
Thank,
Patrick

I know that a 9411 device can run in a SCTL at 40Mhz.
What I don't understand is that I can't run the loop below than 40Mhz.
I read in the FAQ that some device can not run above 40Mhz, but in my case, I want to run in slower....
Can it be because I'm asking the same device to run 1 SCTL with DI0, DI1, DI2 at 40Mhz and 1 other SCTL with DI3 DI4 DI5 at a different loop rate.. (38.75MHz) ...
Thanks,
Patrick

Questions about parallel and series sturcture in SCTL (single clock timed loop) in FPGA VI

I am using LV 8.2.
I have wriiten a FPGA VI, in this VI, there are 3 filters inside the SCTL (single clock timed loop) (I use the shift register to be the effect of unit delay). Would I save the resources of the FPGA used (such as slices and LUT) in the compliation report if I use 3 SCTL ( 1 SCTL contain 1 filter) and cascade them in series?
Thank you!

Sorry, I am afraid that you have misunderstood my meaning.
Here is the method you suggested before:
I mean I use the shift registers attached in the while loop, not in the SCTL. The number of shift registers used will not be decreased when we increase the number of SCTL in the second plate of the flat sequence structure. Totally , there are 6 pairs shift registers for 3 filters (1 filter needs 2 pairs). I mean I put the calculation parts, such as b0*x[n]+b1*x[n-1]+b2*x[n-2] inside the SCTL ( the operations of multiplication and add). Instead of putting 3 filters numeric operation part in one SCTL. will we reduce the resources used if we use 1 SCTL to do the operation parts of 1 filter? As the code inside each SCTL will be reduced.
Maybe you tell me if such approach will reduce the reosources used? Or there is no difference?
Thank you!

Want to use external clock for SCTL on myRIO

Hi people,
I'm trying to find a way to get a 2.5 MSPS 16-bit ADC, TI ADS1602, to send data to the myRIO device. Ideally, I want to record bits at 40 MHz in order to get the benefit of the full 2.5 MSPS. I know that I can create an 80 MHz SCTL on the FPGA to create a 40 MHz clock, but when I checked this clock signal on an oscilloscope it was obviously significantly degraded by slew rate limitations, so it looked more like a sine wave than a square wave. I doubt that it would work to use this signal as a clock to drive the ADC, since the ADC's specifications say the allowable jitter is around 100ps.
I can use an external oscillator to drive the ADC, but then I have to find a way to sync that clock with the 40MHz FPGA clock. Is there any kind of PLL structure that would allow me to sync the myRIO FPGA clock to an external clock? Is there a way to make a single cycle timed loop be driven by an external clock? Or if I was able to customize the FPGA personality to accept an SPI signal of up to 40 MHz (ten times the officially supported limit...), would it be ok to use an FPGA loop running at ~160 MHz and tell it to sample the SPI line each loop and proceed from there?
Thanks!
Solved!
Go to Solution.

Hi 3.14159... ,
The myRIO does not have the ability to import a clock to use on the FPGA Block Diagram to clock single-cycle timed loops (SCTLs). The new sbRIO-9651 that just released at NI Week (not shipping yet) is the only sbRIO that has the ability to import an external clock into LabVIEW. Several of our FlexRIO products also have this ability.
As you alluded to, you can sample the signal at twice the frequency (or possibly more) to and wait until an edge trigger to execute a certain piece of logic. If you open the Example Finder and navigate to Hardware Input and Output » R Series » FPGA Fundamentals » Triggers and Watchdog » Trigger Detection this gives a simple example of doing that. Again, since you are wanting to sample at 10x the supported frequency, all bets are off but it may be worth a try.
Tannerite
National Instruments

How can I use external clock to implement a delay?

Hi all,
I am testing to use external clock to drive dev/PFI0 (on device 6711) which is used as the clock for the analog ouput. I have thinking two applications by using the external clock but I don't have much idea on the implementation yet.
First of all, I have a sequence of data (array) with each sample being sent at the interval of 1us. I use an external clock (10MHz) driving the PFI0 so it is pretty easy to achieve that goal. I am thinking what happen if I want each sampel being sent at different time. For example, if I have 5 samples, I want the first one sent 1us after the task start and wait 2us to send the 2nd sample, wait 5us to send the 3rd sample and wait 11 us to send the 4th sample, and wait 1us to send the last sample. Is it possible to achieve that based on the external clock?
Second question is about the delay. My code require ciritcal timing and the builtin delay doesn't behave very well because I am running in windows. I can increase the priority of the vi to highest, it helps a bit but still not perfect. I am thinking if it is possible to implement hardward delay based on the external clock. Any idea?

Hello dragondriver,
To answer your first question, yes you could send data in that fashion. You would have to programmatically build a pulse train and use that to trigger the sending of data. The answer to the second question is essentially the same. You should be able to programmatically build a pulse train with a delay and use it as trigger to begin whatever operation you have.
Jonathan L.
Applications Engineer
National Instruments

Is the PXIe-PCIe8361 adequate for this system? And external clock questions...

Hi all,
I have spent some time piecing together a system and I'd like a sanity check before pulling the trigger on this purchase. The system will contain the following hardware:
1. Chassis: PXIe-1078
2. Controller: PXIe-PCIe8361
3. 3 x PXIe-6363 (16 analog inputs each card, 32 digital inputs each card, all internally clocked @ 10kHz)
4. 2 x PXI-6224 (32 digital inputs on one, 8 digital inputs on the other, externally clocked in "bursts" of 62.5khz)
5. Labview software
The three PXI-6363 cards will be responsible for a mix of analog and digital measurements made @ 10 kHz, timed continuously by the onboard clock.
One PXI-6224 will be clocked externally @ 62.5 kHz and will be used to collect digital data on a 32-bit port. These clock pulses will not be continuous, but will occur in bursts lasting for 2ms every 20ms.
The other PXI-6224 will be clocked externally @ 62.5kHz as well and will be used to collect digital data on an 8-bit port. These clock pulses will not be continuous, but will occur in bursts lasting for 2 ms at random intervals.
My questions are:
1. Am I planning anything that looks unreasonable for this hardware?
2. Should I expect issues with data transfer rates with the PXIe-PCIe8361? I will be operating well within the advertised 110MB/s throughput of the device. I plan to stream this method... NI Fast TDMS data streaming
3. I have only ever used NI cards for continuous measurements made by an onboard clock. When I set up a task to collect data that is externally-timed, will the DAQ be expecting a "continuous" clock pulse, or will the system wait patiently for clock pulses to arrive at any rate (any rate within the spec of the card, of course)?
Thanks, any input is appreciated.

Hello LucasH0011
1-As long as you put the PXI-6224 and the PXIe-6363 cards in the corresponding slots, meaning the express(PXIe-6363) in the express and the hybrid(PXI-6224) in the hybrid.
2-I think you would not have issues with the transfer rate.
3-Your timing specifications sound reasonable to me, I think you will be fine.
Here is a document that has useful concepts for the use of cards:
http://www.ni.com/white-paper/3615/en/
It is for the M-Series, but the concepts apply to the X-Series as well.
Regards
Ernesto

Using timer/counter with PCI-6221/USB-6210 to control timed-loop VI

Dear all,
I need to ask about two devices and one of their functionalities, PCI-6221 and USB-6210. For our NI-based system, we need to control some timings in a Timed-Loop vi, for that currently we are using PCI-6221 and we give external TTL signal (at 1 kHz) to it,
recenntly we need to make some changes and for that we found USB 6210 DAQ to be more suitable, but we need to clear ourselves on some specific things.
Can the counter/timers functions available in the either PCI 6221 or USB 6210 can be used to control the Timed-loop VI by giving external clock or by using their own internal clock source?
Although we are using external clock with the PCI 6221 but we want to know about the usage of their internal clock, also are controlling timed-loop also possible for USB-6210
Also... What if we use the RTOS, are they still able to control the timed-loop VI without giving any 'EXTERNAL CLOCK' and using the internal clock sources of the DAQs
Waiting for reply,
Bests,
RaJaf
Solved!
Go to Solution.

Ben,
I having read previous email which I send earlier with general overview, we discussed in more detail within our team and I am giviing the specific answers.
Please check in RED the most recent answers. Blue are the questions/suggestions by your side.
1.    Using Internal hardware clock of PCI-6221 would enable us get rid of external clock, but how to divert the internal hardware clock to the current settings. Any idea (can you provide us with some reference manul for otherwise). I mean is there some flag-bit etc. or VI
2.       Is it also meant that with the installation of RTOS the timed-loop can directly get the timing source from the internal hardware clock PCI-6221? --- How???
3.       In order to make desktop to work as RT system, what is the hardware (motherboard, processor, etc..) requirement? What are the LabVIEW modules (specific name) that needed to be installed? Our platform is LabVIEW 8.6. (Currently we have windows-7 with i7 core processor)
What kind of application are you intending for this system? ---- high-speed laser scanning system.
Are you most concerned about accuracy, speed, or responsiveness? To control the laser mirror scanner to move at 1 kHz or 2 kHz speed. On the other hands, using PCI-5105 (128 MB memory) as a DAQ for real-time/on-the-fly data processing.
Bests,
RAJAF

Timed loop

Hi all ! I have a question ...
I have a timed loop (which run on RT target ) . I parameter this loop with 1Khz clock and 1 ms period. The aim of my program is to transmitt/send CAN frames. When i parameter my programm to send a frame every 10s, I receive my frames after 9993 - 9994ms ! I also tested my program with 1 Mhz clock and 1000 µs and i still have the same problem.
I'm almost sure it doesn't come from my program, because i tryed to use an external timing source instead of the internal clock and it works perfectly ! And it can't be beacause my subvi takes too much time, because i receive the frame 6-7ms BEFORE ! It's like the internal clock run faster that it should .... I don't really undrstand, could someone help me ???
Thanks...

Hi,
I can't believe that the use of the 1MHz clock can give this result but the timing must be always accurate using the 1KHz clock.
I don't think the timed loop itself is the problem. Are you using a timing function or tick count function in your VI or subVIs?
Are you using a PXI target? because it seems that the timed loop is not accurate only in PXI.
Investigate and let me know.
Regards.
Omar S. NI

CVS-1458RT - ISO I/P triggered timed loop

Hi everyone,
I am developing a real-time machine vision application on a CVS-1458 RT.
What I am aiming is a timed loop that is triggered via external clock (in my case a photoelectric sensor connected to an ISO input). All examples I can find are related to DAQmx devices, nothing related to visionRIO.
Question 1: Is this the best way to construct the acquisition loop? I want it to be condition based as to free-up the CPU from continous polling. If not, wht is the best way ?
Question 2: If the above method is OK, how can I setup the input node of my timed loop in a way to implement this ?
Thank you,
Omar

Hi Omar,
I was able to find some Vision-RIO examples in the Example Finder of LabVIEW. If you open LabVIEW and navigate to Help>> Find Examples.
In the Example Finder in the Browse tab navigate to Hardware Input and Output>> Vision Acquisition>> Vision-RIO.

External clock LabView crash with Measurment Computing board.

Hi,
I'm using a Measurment Computing PCI-DAS6402-16 board with Labview (using Universal librarys VIs) in a 4-stroke engine DAQ application and amognst the signals obtain Internaly clocked, there is In-Cylinders Pressure signal which is timed with a Crank-angle deocoder sending analog pulse signal.
Although there seems to be no problem while the motor is running, it appears that when to external clocked signal is not getting any pulses (while the motor is not running) then Labview stops to respond and awaits for the external clock to start, and that doesnt happen within 10s then it crashes.
I dont know whether it is Software problem (because external and internal clocked signals are both in the same WHILE LOOP) or if it is a Hardware problem (because With a NI card there seem to be no problems).
THNX in Advance

Well it couldnt be a more typcal windows crash:
If a channel is externally timed with an analog pusle signal, If the VI starts running but the external clock isn't then:
-Labview stops to respond to any clicks (there is no .exe at this point) but it keeps working though (That i know cause if i start the ext. clock at this point it "un-stucks' and starts working)
-But, if for some secs no ext. pulse signal is generated then labnview app stops respondin and i get the typical 'send error report' window.
Could it be that the Universal library for Measurment Computing boards haw a bug? Cause the same thing happens with the "Analog input External Clock.vi" example given with the Library..so it can't be my mistake..or can it?!

Reading digital port with external clock at maximum speed

I have a PCI-6509. I am programming a fast loop to read 32 bits values from the digital input using an external clock ( injected into one of the card pin inputs )
The environment is Windows2000 + Visual C++ .
basically I am doing
DAQmxErrChk (DAQmxCreateTask("",&taskHandle));
DAQmxErrChk (DAQmxCreateDIChan(taskHandle,"Dev1/port0:3","",DAQmx_Val_ChanForAllLines));
DAQmxErrChk (DAQmxSetSampTimingType(taskHandle,DAQmx_Val_ChangeDetection));
DAQmxErrChk (DAQmxCfgChangeDetectionTiming (taskHandle,"/Dev1/port5/line4:4", NULL, DAQmx_Val_FiniteSamps , sampsRequested));
DAQmxErrChk (DAQmxStartTask(taskHandle));
getSystemTime...
DAQmxErrChk (DAQmxReadDigitalU32(taskHandle,-1,-1,DAQmx_Val_GroupByChannel,data,sampsRequested,&sampsRead,NULL));
getSystemTime...
I pass a data buffer big enought to hold the number of samples I am requesting ( for example 10000 of uInt32 ).
It works fine. I get my values but the speed I get is only around 10 KHz.
I print the system time before and after the call to DAQmxReadDigitalU32 as you can see from the above code.
This makes no sense because my external clock in ,"/Dev1/port5/line4:4" (as selected on the ChangeDetectionTiming call) runs at 2.0 MHz.
Could someone tell me what parameters I have to pass to this sequence of NI DAQ functions calls in order to really read at the speed of my external clock?
many thanks in advance,
Roberto AButer.
Note :
I am going desperate with the web pages, documentation , online helps and the pletora of products and so on.
I did pay to NI a considerable amount of money for the card , the labview software etc and I just want to do the simplest 20 lines C program to read my digital signal at the speed is being injected. Should that be that difficult????

Hello caca,
the board you are using is specified as a static IO board. That means it was not constructed to do highspeed DIO operations.
You cannot use a hardware clock to time your input and output
operations, so you have to use a software timing or, as you chose, the
change detection interrupt. But the maximum speed you can archieve
doing this, is somewhat limited of course.
Check this thread for some more information.
Ingo Schumacher
Systems Engineer Sound&VibrationNational Instruments Germany

How do I use a quadrature encoder as an external clock (PCI 6229)

Hello, ( a similar post has been placed on DAQ forum apologies as I did not know best place)
I have a PCI 6229 M Series data acquisition card. I want to use a quadrature encoder to be the external clock driving the acquisition of a number of signals. I have set up reading 24 signals each time a clock pulse is received using the DAQ assistant and set my external clock to pin pfi8 (I think) this is then connected to an encoder output. This works well enough until the encoder is run too fast when it appears I am either missing pulses or getting bounce.
How can I set up to clock using a quadrature encoder? I have seen a number of questions on this forum regarding quadrature encoders and reverse counting but not on using them as an external clock.
Basically I want to have the stability and "bounceless" nature of using two outputs from a quadrature encoder whilst still using an external clock. Is this just a case of configuring controls to certain pfi's? If so how is it done?
Any help or pointers would be helpful. So far I have managed very nicely by simply using the DAQ assistant and the interface it has would suggest that if configured for a certain pfi pin I could actually still use it.
Thanks in advance.
Kevin

Hi,
Well I've had alook into this for you and I'm not quite sure I understand what you are looking for.
Is it possible for you to phone back in to support?
The reason you are seeing bounce at high speeds, or indeed loss of points, is due to the sampling rate that you have set up.
What you will find is that the trigger will start an aquisition of a number of points at a certain rate. If your sampling rate is too low then you will not finish that sample batch before the next set of samples is recorded.
It is possible to use an external clock into a trigger or digital line, however this will limit the number of samples you can take to the speed of your encoder.
If you increase your sampling rates, and then configure a start trigger from a single input from the encoder you will be able to record a number of samples after a rising/falling edge. (Set the clock as an internal clock)
Hope this helps
AdamB
Applications Engineering Team Leader | National Instruments | UK & Ireland

LabVIEW RT, Timed loop, finished late, Call by reference

I have a timed loop triggered by the sample clock of a DAQ-Card. The sample Clock is 8 kHz and the loop will run with dt = 4. Normally the loop is running without finished late[i-1]. But from time to time it happens that the loop is running extremly longer which means instead of 0.5 millisec it needs 4 - 5 millisec. It seems this doesn't never occur while accessing DAQmx.
The application uses plugin technologies and some of the VIs in the timed loop are preloaded and called by Call by Reference.
Does those VIs inherit the priority, execution system and CPU of the timed loop?
The application is running on LV RT 2009 on a Dual core PXI-Controller. The timed loop is bound to CPU 1. There is no difference runinng the application from the development environment or as a startup application.
For the measuring test I modified the application in a way that I don't have:
disk access for storing the result file
TCP/IP communication
Controls on the front panel of the top level VI
Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

To keep you informed:
I stripped the application and have left only the measurement storing module and the timed loop. The loop was using the microsecond timer running each 500 µsec. Additional all Non-Real-Time modules were loaded and only one module creates a XML string and sends it to the communication layer which will drop it because no TCP/IP port is open. The creation of the XML string is done each 300 ms.
In this case I don't have any finished late iterations
Next I added the DAQ Module. Now I get finished late again but with a lesser frequency as original.
I removed all unnesseccary tasks from the DAQ moulde leaving one task for a PXI-4204 for using as the clock source for the timed loop. No I get finished late seldom.
I removed the module which will send the XML string and I don't get finished late.
Next I was adding code to see memory allocation. I can when memory allocation is changing but it is not related to the finished late iterations.
Next time I have the chance to do more tests I will see which DAQ task triggers the finished late iterations. I have one AI task on a PXI-4204, 4 Counter tasks on a PXI-6602, 1 DI task on a PXI-6514, 1 DO task on a PXI-6514, 1 DI task on a PXI-6259, 1 DO task on a PXI-6259, 1 AO task on a PXI-6259 and 1 AO task on a PXI-6711.
The AI task on the PXI-4204 is running in Continous Sampling (Single Point HW Timed is not supported), all other tasks exept the DI and DO are Single Point HW Timed.
Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

CRIO rt timed loop w/ external clock trigger???

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