Failing timing when making small, unrelated change - what can I do?

Question

I have a Spartan 6 that is mostly clocked at 60MHz, but has one section that is clocked at 240MHz (along with 60MHz). That section is very separate from everything else.
Today I tried to add in a new module to my project. It is a SPI slave controller - essentially it takes a SPI command and writes to or reads from a couple of registers. Very simple. The instantiation of it has only 6 ports - the 4 SPI lines (MISO, MOSI, SCK, and nCS), reset, and clock (60MHz). The SPI lines are directly connected to pins on the chip.
Adding this in makes me start to fail timing in the 240MHz section.
Again, the only connection between the new section and the old section is the 60MHz clock and the reset line.
Can anybody suggest what I might look at to try to start meeting timing again? Or perhaps are there options within ISE that I can play with?
I can share (privately) the code - but I suspect that that would be time consuming for somebody to look at.
Thank you!

Answer 1

Id start by wading through the warning messages 
there will be a bunch, and as a rule I'd make certain I have either fixed them or at least know I can't fix them and why they are happening.
The sartan 6 is a great part, but it does suffer with restricted clocking capabilities.
    its easy to end up putting clock in on the wrong side etc.
and 240 MHz is pushing the Spartan 6  part, just the movment of the 240 MHz blocks around the chip could have killed your performance. How full is the chip ?
make certain your using all the fast helpfull bits you can, 
   like the built in registered rams, not asyncronous, the IOB registers, 
then its down to looking at the timming reports, the layout and your constraints, 
the none magic is to up the amount of effort the tools put in,
    but unless this is the absolute last build , that is but a stop gap answer.