Fpga-vhdl

Bonjour,
Une chose me tracasse et j' aimerais avoir des éclaircissements.
Lors de l' exécution Labview transforme son code graphique en vhdl puis de vhdl en Bitstream
Labview étant synthétisable , peut on récupérer le code vhdl et le compiler sur un autre logiciel comme model sim ,simplorer..etc
Si oui , je crois qu' on est pas obligé d' utiliser une carte ni pour configurer FPGA.
Merci d' être explicite, afin que d' autres puissent bénéficier des réponses
Solved!
Go to Solution.

Bonjour,
Le schéma de compilation LabVIEW FPGA est propriétaire et donc fermé.
Autrement dit, il n'y a pas moyen de récupérer les fichiers VHDL intermédiaire.
Ceci est illégal, et propriété de NI
Bonne journée
Bien cordialement
Victor F. | Application Engineer
Certified LabVIEW Developer | Certified TestStand Architect
National Instruments France

Similar Messages

LabView fpga VHDL code and compiler

Hello,
I'm in the project where we would like to use NI hardware (more likely cRIO system). With NI hardware we will read/wright several AI/AO and DIO and perform some math and controls on the result of readings. We are planning to design FPGA code for project, but we are thinking about implement all data processing and control logic in VHDL and link it with AI, AO and DIO with help CLIP or IP Integration Node as explained in this : "white-paper": http://www.ni.com/white-paper/7444/en/
Mentioned above paper explain how to implement VHDL code in LabVIEW FPGA VI using CLIP or IP Integration Node, but the topic that is not highlight explicitly is how these construction CLIP and IP Integration Node will be handled by Compiler. The main reason for such approach (VHDL linked with part that read/write into hardware AI AO and DIO) we expect that our VHDL code will be handled by LabVIEW compiler without modification and passed to Xilinx Compiler synthesis as is (path for Compile process I've taken from here: http://www.ni.com/white-paper/9381/en/ ), so we will be able at some level bypass the intermediate process of compilation and get almost the same result as if we design pure VHDL code and use Xilinx ISE for Synthesis Mapping and Bit File generation.
Will this approach work? I was not able to find any documents that explain the Compiler behavior and confirm that VHDL code handled untouched or will modified, does such document exist?
Note. I've requested official assistance from NI support on topic above, but I would like to post this question on forum hoping get more feedback.

Hello RangerOne,
There won't be any modications to the internal logic of the VHDL that you implement in the IP integration node. Though I've seen developers unfamiliar with LabVIEW FPGA get tripped up on the synchronization registers that LabVIEW FPGA inserts into the code around the integration node. Learning where and why these syncrhonization registers are inserted has in my experience always resolved this issue. These two help documents do a good job of explaining the 'where and why' of synch registers when the enable chain is present, or when working with IO inside of a SCTL.
With regards to the stability of LabVIEW FPGA, I would second Daniel's sentiments. What about the known issues list conveys instability and risk? As a point of comparison, here are the known issues for ISE 14.x.
If you are looking to minimize risk, I would recommend developing the critical logic in the development enviroment in which you are comfortable setting up a comprehensive test bench since testing the code is the only way to truly verify its functionality. For me this would be LabVIEW FPGA as it has excellent trouble shooting tools and I've been developing in it for quite some time. Perhaps you're more familiar with ISE than LabVIEW FPGA and that is the source of your trepidation? If that is the case then you may find the High Performance FPGA Developers Guide a good read. You may also find a few of the case studies on our website reassuring since they demonstrate other teams successfully implementing a solution using LabVIEW FPGA. Here's one that used LabVIEW FPGA in conjnction with VHDL IP similiar to what you are doing.
National Instruments
FlexRIO Product Support Engineer

Fpga VHDL import in Labview

Hello,
I have to import VHDL code in Labview. I would like to know what is the best solution betveen CLIP, IP Node integration or HDL node of the previous version of Labview if it is possible to use it.
Thank you
Solved!
Go to Solution.

Hello,
I think those documentations will help you to choose, depending on your requirements:
Difference Between CLIP Node and HDL Node
CLIP and IP Integration Node Differences
Regards,
Mathieu P. | Certified LabVIEW Associate Developer
National Instruments France
#adMrkt{text-align: center;font-size:11px; font-weight: bold;} #adMrkt a {text-decoration: none;} #adMrkt a:hover{font-size: 9px;} #adMrkt a span{display: none;} #adMrkt a:hover span{display: block;}
Journées techniques : des fondamentaux aux dernières technologies pour la mesure et le contrôle/comm...

Averna - Hardware-FPGA Designer - Atlanta, GA Area.

Hardware-FPGA Designer
Averna is a test engineering company providing software solutions and services worldwide.
Averna's mission is to accelerate electronic product development and quality improvement with a clientele working in the fields of electronics, telecommunications, automotive, aerospace and defense. Averna’s impact echoes throughout its entire lifecycle of products, from the design phase to manufacturing.
We offer a stimulating, dynamic and casual working environment, with interesting challenges for candidates wishing to progress in their career.
Job Summary
As a member of the Systems and Services team, you will be involved in the design and development of customer driven FPGA solutions in both LabVIEW FPGA and VHDL.
Responsibilities
Developing LabVIEW FPGA models
Developing VHDL models
DSP based algorithm development
Technical Writing
Any other related duties
Qualifications
Bachelor of Electrical Engineering, Computer Engineering or equivalent;
Minimum 4 years experience FPGA development;
Very good knowledge of programming FPGA, VHDL and C + +;
Very good knowledge of DSP processors and the process of signal processing;
Experience in technical writing;
Ability to travel occasionally;
Professionalism, strong communication and interpersonal skills, resourcefulness, autonomy.
To apply, please submit your application to: [email protected] indicating the job title.
We thank you for your interest in our company but only selected candidates will be contacted.

Will you consider applicants outside the US?

NATIONAL INSTRUMENTS LABVIEW REALTIME V6.1, NI-488.2 V2.01, CNC CADCAM

IAR, NATIONAL INSTRUMENTS LABVIEW REALTIME V6.1, NI-488.2 V2.01, CNC CADCAM
IAR,
Microwave Design Office 2002, Cadence, OrCAD, Protel, FPGA, VHDL,
Natinst, Xilinx, Siemens Simatic, Labview, metrowerks codewarrior8
[2CDs],
other 20 gigabytes/week software for pc and mac
send email for catalogue

Hello,
Which driver have you on your computer ? You can see them in MAX >> Software. Which is version of ni-visa, ni-488.2 ?
What kind of protocol do you want to use : gpib, serial, parallel ?
What ahhpens in AMX when you test your communication ?
What are error code and error string ?
Regards,
Isabelle
Ingénieur d'applications
National Instruments France

DC to DC converter basics using Labview on FPGA Control with VHDL

DC to DC converter basics using Labview
I am fairly a novice, that is why simplifications required, before I begin thanks in advancefor them who will response
I am designing a DC to DC (Intermediate Bus Converter, a step down BUCK converter, of 24 v input and output 9 v and 5 amp current output), using FPGA controller, I need to program this using VHDL, for which I take LabVIEW, but as I am new so do not have any idea as what are the steps that I need to take for implementation, what types of function that FPGA does in this so that it can generate 24 v and what other mechanisms that have to control inside or outside of FPGA programming and designing that it can give the desired output voltage, if you have any idea about this then I would be glad to receive the steps that are necessary to complete this

NI supports two Spartan 3E products through either LabVIEW FPGA or MultiSIM, the Digital Electronics FPGA Board (http://sine.ni.com/nips/cds/view/p/lang/en/nid/207010) and, if you are in academia, the Xilinx Spartan 3E XUP starter board (as linked by Dennis_Knutson).
Also note that if you wanted to implement some logic in VHDL and have access to that logic in a LVFPGA diagram, you could utilize the Component-level IP (CLIP) fuctionality (http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/using_component_ip/)

FPGA compiler Server status says idle but Status says compiling VHDL

when i compile my FGPA vi file , after some time in the compile server window "Server status" shows "idle.." but the status box shows "Compiling VHDL".
It stays in this condition for a long time about 30 mins. Why is this happening? I am also attaching the screenshot of the compile server.
FPGA vi i am trying to compile is the Sine Generator.vi which was there in examples under FPGA Fundamanetals->Analysis and Controls.
Attachments:
compile server.JPG ‏59 KB

I am attaching the block diagram of the fpga vi. It is a sine generator example which was in the labview examples folder.
I am seeign this behaviour only when i compile this fpga vi. I have compiled other fpga vi's without any problem.
Attachments:
fpga vi for sine genrator.JPG ‏127 KB

Can I export VHDL from Labview FPGA?

Hello,
We have a situation where existing Labview FPGA code works, but we need
to embed it into an environment where we can't run Labview. So
we're considering taking the VHDL generated by Labview FPGA and porting
it to another FPGA.
To do that, we need to get our hands on the VHDL output. How does one do that?
Thanks,
Peter H.
PS: If could find an FPGA forum, I would post my question there...

Hi M.,
yes, there is a translator to C. Just call your local NI representative. Take a seat before asking for the price
Best regards,
GerdW
CLAD, using 2009SP1 + LV2011SP1 + LV2014SP1 on WinXP+Win7+cRIO
Kudos are welcome

Decriptare codice vhdl generato da labview FPGA

Salve,
quello che sto cercando di fare è di aprire un file vhd generato da labview FPGA durante la compilaizione di un VI, per vedere come viene scritto il codice. Questo perchè mi piacerebbe poterlo confrontare con un identico codice scritto direttamente in vhdl...

Salve,
non è possibile accedere al codice vhdl generato da LabVIEW FPGA durante la compilazione.
LabVIEW è stato sviluppato proprio per evitare la scrittura/analisi di codice vhdl testuale.

FPGA Code Generation fails with error codes 7 and -1

Hi all,
I have been having a weird issue with my LV FPGA compilation in the last couple of days, no matter what I try to compile LV fails to generate the FPGA code files and returns with errors 7 and -1 and complains that the file is not found. This happens no matter what I am trying to compile even a VI with just a while loop. I followed the discussion forum here without any luck, also followed the NI article here and that did not help either. The error codes always get generated at the start of the Generating Intermediate files step #7 (out of 7).
Attached to this post is a screenshot of the error I am getting (error -1 just says internal error and to contact NI support), bellow is basically the error I get for error code 7
An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with the following information:
Error 7 occurred at Read from Text File in nirviGetInstantiation_cRIO-IDSel_Timer.vi->nirviGetInstantiation_cRIO-IDSel_Timer.vi.ProxyCaller
Possible reason(s):
LabVIEW: File not found. The file might have been moved or deleted, or the file path might be incorrectly formatted for the operating system. For example, use \ as path separators on Windows, : on Mac OS X, and / on Linux. Verify that the path is correct using the command prompt or file explorer.
=========================
NI-488: Nonexistent GPIB interface.
C:\NIFPGA\compilation\cRioController_8-SlotFPGA_FPGA-TriggerTest_C06156E2\IDSel_Timer.vhd
I tried to do some digging to see what could possibly be happening, and I noticed that LV is looking for the vhdl files in the wrong folder (see the line highlighted in red above), when generating the vhdl files, LV will place them inside the "source_files" folder under the compilation project, but for some reason it is trying to find them under the root folder not inside the source_files folder!!!
Does anyone have any idea why LV would be looking for these files in the wrong subfolder?
Thank you,
Aws
Attachments:
Code Generation Errors.png ‏35 KB

Hi Aws_Khudhair,
What version of LabVIEW are you using? And what version of the FPGA module? From what I found, it seems as though this is primarily an issue with LabVIEW 8.6 and 8.6.1.
http://digital.ni.com/public.nsf/allkb/A711119FE89E39E78625754E00075E92
This forum also discusses a similar issue:
http://forums.ni.com/t5/Real-Time-Measurement-and/FPGA-compile-errors-after-generating-intemediate-f...
It may also be worth repairing/reinstalling the FPGA Module and the Xilinx compile tools.
Catherine B.
Applications Engineer
National Instruments

If i have a LV FPGA program, will i be able to get a wiring list for that program so that i can download it into some other FPGA?

after doing rapid control prototyping using 7831R and LVFPGA, if i decide to build the custom chip, can i use the LV code that i've alredy built or i'll have to do the coding again in VHDL
KAliDas

The LabVIEW FPGA module currently does not expose the VHDL code to you and will not download the code to non-NI hardware. However, it will allow you to quickly provide a 'proof of concept' if you are planning on using a custom chip in the future.
Regards,
JR A.
Application Engineer
National Instruments

Access to serial and ethernet port in FPGA for cRIO-9068

hi
i want to know if i can Access to serial and ethernet port in FPGA for cRIO-9068 like camera IP
thanks for help

dalyto wrote:
thanks
but how i can i acquire image with IP camera and fpga ???
The Ethernet hardware interface in the cRIO is not directly connected to the FPGA backplane in a way that you could directly access it. Even if you could it would be a pretty bad idea to try to do. A fully operational TCP/IP network stack implementation in the FPGA would not leave much resources for anything else even on the biggest FPGAs available. That doesn't include support for the typical image compression algorithmes which are even more complicated to implement on FPGA. Even if you would go to highly optimized VHDL code directly it would be a pretty difficult thing to do!
In fact implemenintg the MAC and PHY of an ethernet interface on the FPGA is totally trivial in comparison. The IP level could also be implemented fairly easily in the FPGA but anything above that is going to give you bad headaches and still will be very limited in number of connections and packet sizes it can support.
Rolf Kalbermatter
CIT Engineering Netherlands
a division of Test & Measurement Solutions

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

Labview FPGA for beginners.

Hello.
I have no idea what labview is and how to work with this. I have had some experience with Xilinx 12.1 EDK (microblaze and VHDL).
I tried to install labview and labview fpga module. It asked for some drivers and I continued, the program said that it will ask for the drivers later.
But, beside that, do you have any training flow to suggest? Should I start with labview or is it not necessary? After that, should I start with CVI or FPGA? I am confused. Any help is welcomed!
Thanks,
Bill.

See this video's to get start with labVIEW and more video's you can find in youtube. Also, get in touch with forum especially about FPGA questions or read the history question targeting to your design area.
http://zone.ni.com/devzone/cda/tut/p/id/7466
I never use FPGA codes or concepts in labVIEW but I am looking to learn now.

Labview fpga development board

hi all
can i programme my own development board having xillinx fpga using labview fpga .. or lab view fpga can only be used by national instruments hardware ?
Regards

Just to reiterate what was already said, The LabVIEW FPGA generates VHDL code that can not be used or downloaded into non-NI hardware, even if it uses the same Xilinx FPGA.
That being said, there is one board that you can use that is not National Instruments, Xilinx SPARTAN-3E XUP Starter Kit
Regards,
Andrew Eddleman
National Instruments
RIO Embedded Hardware PSE
CompactRIO Developers Guide

Fpga-vhdl

Similar Messages

Maybe you are looking for