FPGA compiler Server status says idle but Status says compiling VHDL

Question

when i compile my FGPA vi file , after some time in the compile server window "Server status" shows "idle.." but the status box shows "Compiling VHDL".
It stays in this condition for a long time about 30 mins. Why is this happening? I am also attaching the screenshot of the compile server.
FPGA vi i am trying to compile is the Sine Generator.vi which was there in examples under FPGA Fundamanetals->Analysis and Controls.
Attachments:
compile server.JPG ‏59 KB

Answer 1

I am attaching the block diagram of the fpga vi. It is a sine generator example which was in the labview examples folder.
I am seeign this behaviour only when i compile this fpga vi. I have compiled other fpga vi's without any problem.
Attachments:
fpga vi for sine genrator.JPG ‏127 KB