Labview FPGA for beginners.

Hello.
I have no idea what labview is and how to work with this. I have had some experience with Xilinx 12.1 EDK (microblaze and VHDL).
I tried to install labview and labview fpga module. It asked for some drivers and I continued, the program said that it will ask for the drivers later.
But, beside that, do you have any training flow to suggest? Should I start with labview or is it not necessary? After that, should I start with CVI or FPGA? I am confused. Any help is welcomed!
Thanks,
Bill.

See this video's to get start with labVIEW and more video's you can find in youtube. Also, get in touch with forum especially about FPGA questions or read the history question targeting to your design area.
http://zone.ni.com/devzone/cda/tut/p/id/7466
I never use FPGA codes or concepts in labVIEW but I am looking to learn now.

Similar Messages

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

Xilinx version availability for labview fpga compile

While trying to compile a Labview vi for target NI PXI 7831R, at first I didn't have
any Xilinx compile so I asked my network guy to instal it. Now it complains
that it needs 10.1 when 11.5 is available. I asked him to install the 10.1 and
he did but it isn't available to the NI FPGA compile worker. How do I solve
this?
thanks

Hi DonQuixote,
You are correct in that the PXI 7831R requires Xilinx Compile Tools 10.1. This is because this card has a Vertex II chip. You can read more about Xilinx requirements here: http://ae.natinst.com/public.nsf/webPreview/A4B20D58C051DFB386257A56007BB0B2?OpenDocument .
Have you uninstalled version 11.5? What version of LabVIEW do you have? Are you recieving an error or some other message? If so, please post a screenshot.
Thanks!
Dayna P.

LabVIEW FPGA driver for Xilinx SPARTAN 3E Starter Board

i need drivers for spartan 3E .

If you are at a university that has a site license for the FPGA module, the following might be of interest to you:
Using LabVIEW FPGA with the Xilinx SPARTAN-3E XUP Starter Kit
See also this discussion.
Quote from the license agreement:
...INSTALLATION AND USE OF THE LABVIEW FPGA TARGET MODULE FOR THE XILINX SPARTAN-3E STARTER BOARD (THE “TARGET MODULE”) IS LIMITED TO ACADEMIC INSTITUTIONS THAT HAVE A VALID, CURRENT “ACADEMIC TEACHING LICENSE” FROM NATIONAL INSTRUMENTS FOR THE LABVIEW FPGA MODULE. THIS TARGET MODULE MAY ONLY BE USED FOR INSTRUCTIONAL PURPOSES, SUBJECT TO THE TERMS AND CONDITIONS OF THE NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT THAT ACCOMPANIES THE SOFTWARE...
LabVIEW Champion . Do more with less code and in less time .

LabVIEW FPGA PMW modulation for L298n H-bridge

Hello to everyone,
I am new in LabVIEW FPGA programing and I have a couple questions, so I would be grateful if you could answer me. For my final work I have to control the speed and direction of DC motor using sb-RIO 9636 and H-bridge L298n. In attachments you can find scheme of the H- bridge and my program. I have conected In1(pin 5 of L298n) to digital pin 1 of the card, In2(pin 7 of L298n) to digital pin 2 of the card and changing the state of the pin I change the direction of the motor(I know that the one In should be Low and the other High so the motor can rotate in one or the other direction). PWM(Enable pin of the L298n pin 6) I have conected to DIO3.
PWM signal I cretaed is shown in picture.
My questions are:
1.Will loop timer I used, provide that period of signal is lenght I specify in the control(for example if I put 20 000 will the period be 20000 s)?
2. Can I vary the duty cycle changing the control Waiting (DIO3 is HIGH for a couple of us, then it sets LOW, and then all that repeats )?
3. Earlier I thaugt that PWM signal I should send in both IN1 and IN2, and that the Enable pin is used to stop or start the motor. I tried that and the motor was rotating different speed, and I could stop or star the motor with enable pin, sending it HIGH OR LOW, but I could not change the direction of the motor. So my other option was to conect the pins as I explained at the begining. My question is: Should I PWM conect to the enable pin, and will thah work?
Thank you

I found a couple of resources that deal with PWM on the FPGA and motor control - they might be helpful to reference as you look for answers to your questions.
Developing a PWM Interface using LabVIEW FPGA
http://www.ni.com/white-paper/3254/en/
CompactRIO Motor Control Basics Tutorial
http://www.ni.com/pdf/labview/us/compactrio_motor_control_basics.pdf
PWM Output With LabVIEW FPGA
http://www.ni.com/example/26499/en/

Need SPARTAN 3E board Driver for Labview FPGA 8.5 !!!!!! Thx

HI!!I need the spartan 3e driver for labview 8.5(not for labview 8.6) for school useI try to download it from ftp://ftp.ni.com/outgoing/NISPARTAN3ELV85.zip
but this link is dead now. Could somebody send this driver to [email protected] PLZ? Thank you a lot for all in advance
Solved!
Go to Solution.

Hello,
I'm looking for same (Labview FPGA 8.5 for Spartan 3E). But it isn't available on related url now. I'll be glad if someone can help to find driver.
Best regards,

C API version required for LabVIEW FPGA 2011

What is the verison of the C API that will work with LabVIEW FPGA 2011?
Solved!
Go to Solution.

I would guess this one: http://www.ni.com/download/fpga-interface-c-api-2.0/2616/en/
The version numbers appear to start with years in 2012. This is the highest version I could find before 2012 and it was released in August of 2011. That time coincides with the annual NI Week festivities where a large portion of the software/hardware is released. It's a small download so it shouldn't be difficult to download and try it out.
But, you'll still need LabVIEW for FPGA development according to this white paper: http://www.ni.com/white-paper/9036/en/

Can anyone provide me the suitable material for labview fpga &labview real time??

Message Edited by Sithu on 05-27-2008 04:32 AM

The following link includes training material for both LabVIEW Real-time and LabVIEW FPGA.
http://zone.ni.com/devzone/cda/tut/p/id/6929
If you are new to LabVIEW you should start from the LabVIEW Basics material available at the following link.
http://cnx.org/content/col10241/latest/
KostasB
NIUK Applications Engineering

DCT for Labview fpga

Hi,
I have problems based on dct for labview fpga. I get the project example from this link https://decibel.ni.com/content/docs/DOC-8202. I run the project in labview and its run succesfully. After that, I try to use a different vhdl code for the CLIP (in labview) that I get from open cores (http://opencores.org/project,dct_idct). I rewrite the fpga.vi by inserting a new vhdl code in the CLIP. When I run the project, there are no errors. However, the compressed image is not display. I check the output values from the Read from FPGA block at the host.vi and it shows zero values at all time. I try to debug, but still don't get the solution. Anyone expert please help me. Thanks in advance.

Hey Troy,
Have a look at the attached front panel design that will be compatible in FPGA.
Hopefully it helps!!
Aashish M
Applications Engineer
National Instruments
http://www.ni.com/support/
Attachments:
FPGA_CALC.vi ‏22 KB

Need spartan 3e driver for LabVIEW FPGA 2011

Hello,
I'm looking for Spartan-3E driver for Windows 7 LabVIEW FPGA 2011.
Thank you

Thank you for all the helps. I do appreciate that.
By the way, I'm wondering the latest driver on NI is used for Labview FPGA 2012 or 2012sp1?
Just in case our department would purchase the latest version of Labivew in the near future.
Thank you again and have a nice day.

How to use LabVIEW FPGA on Custom FPGA board other than NI products .....Also how to develop RTx DLL for a customised motion controller hardware

I'm using RTx, LabVIEW RT and LabVIEW FPGA.
The GUI is windows based. The motion control and FPGA are RTx based.
Is there any way to develop device drivers for the custom hardware in RTx. For example motion controller hardware, FPGA hardware, PCI hardware.
Is there a possibility to use custom FPGA boards to use with LabVIEW FPGA.
Please send me some links
Thanks
Bhoopathy
Take life as it comes! you may never know what's gonna happen Tommorrow

CODE WARRIOR Hello. I believe this question was answered in a previous post. Please let us know if you have any new questioins or if you need some clarification.
You are able to develop device drivers for your custom hardware using the NI Measurement Hardware Driver Development Kit.
However, it is not possible to use custom FPGA boards with LabVIEW FPGA. The FPGA boards have to be one of our R Series boards. Here are some links that should shed some light on the Measurement Hardware DDK.
Measurement Hardware Driver Development Kit Frequently Asked Questions
NI Measurement Hardware DDK (Driver Development Kit)
Please post if you have further questios.
Efosa O.
NIAE

Why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?

Dear Friends,
Since I have started using LABVIEW FPGA, I got too many questions in my mind looking for answers!
1-      Does anybody can tell me “why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?”
I mean there are many great tools in this field (e.g. Xilinx ISE, ….); what makes LABVIEW FPGA the perfect tools that can save my time and my money?
I’m looking for a comparison can show the following points:
·         The Code size and speed optimization.
·         Developing time.
·         Compiling time.
·         Verifying time.
·         Ability to developing in future.
·         …etc.. 2-
I’ve Spartan-3E kit, I’m so glad that LABVIEW support this kit; I do enjoyed programming the kit using LABVIEW FPGA, but there are too many obstacles!
The examples come with Spartan-3E driver don't cover all peripherals on board (e.g. LAN port is not covered)! There is a declaration at NI website which is "LabVIEW FPGA drivers and examples for all on-board resources" Located at: http://digital.ni.com/express.nsf/bycode/spartan3eI don’t think that is true!
Anyway, I will try to develop examples for the unsupported peripherals, but if the Pins of these peripherals are not defined in the UCF file, the effort is worthless! The only solution in this case is to develop VHDL code in ISE and use it in Labview FPGA using HDL node!?
3-      I wonder if NI has any plan to add support for Processor setup in Labview FPGA (Like we do in EDK)?
4-      I wonder if NI has any plan to develop a driver for Virtex-5 OpenSPARC Evaluation Platform ?http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,599&Prod=XUPV5
Thnaks & regards,Walid
Solved!
Go to Solution.

Thanks for your questions and I hope I can answer them appropriately
1. LabVIEW FPGA utilizes the intuitive graphical dataflow language of LabVIEW to target FPGA technology. LabVIEW is particularly nice for FPGA programming because of its ability to represent parallelism inherent to FPGAs. It also serves as a software-like programming experience with loops and structures which has become a focus of industry lately with C-to-gates and other abstraction efforts. Here are some general comparison along the vectors you mentioned
Code Size and speed optimization - LabVIEW FPGA is a programming language. As such, one can program badly and create designs that are too big to fit on a chip and too slow to meet timing. However, there are two main programming paradigms which you can use. The normal LabVIEW dataflow programming (meaning outside a single-cycle loop) adds registers in order to enforce dataflow and synchronization in parity with the LabVIEW model of computation. As with any abstraction, this use of registers is logic necessary to enforce LabVIEW dataflow and might not be what an expert HDL programmer would create. You trade off the simplicity of LabVIEW dataflow in this case. On the other hand, when you program inside a Single-Cycle timed loop you can achieve size and speed efficiencies comparable to many VHDL implementations. We have had many users that understand that way LabVIEW is transformed to hardware and program in such a way to create very efficient and complex systems.
Development Time - Compared to VHDL many of our users get near infinite improvements in development time due to the fact that they do not know (nor do they have to know) VHDL or Verilog. Someone who knows LabVIEW can now reach the speeds and parallelism afforded by FPGAs without learning a new language. For harware engineers (that might actually have an alternative to LabVIEW) there are still extreme time saving aspects of LabVIEW including ready-made I/O interfaces, Simple FIFO DMA transfers, stichable IP blocks, and visualizable parallism. I talk to many hardware engineers that are able to drastically improve development time with LabVIEW, especially since they are more knowledgable about the target hardware.
Compilation Time - Comparable to slightly longer to due to the extra step of generating intermediate files from the LabVIEW diagram, and the increased level of hierarchy in the design to handle abstraction.
Verification Time - One of our key development initiatives moving forward is increased debugging capabilities. Today we have the abilities to functionally simulate anything included in LabVIEW FPGA, and we recently added simluation capabilities for Imported IP through the IP Integration node on NI Labs and the ability to excite your design with simulated I/O. This functional simualation is very fast and is great for verification and quick-turn design iteration. However, we still want to provide more debugging from the timing prespective with better cycle-accurate simulation. Although significantly slower than functional simulation. Cycle-accuracy give us the next level of verification before compilation. The single cycle loop running in emulation mode is cycle accurate simluation, but we want more system level simulation moving forwrad. Finally, we have worked to import things like Xilinx chipscope (soon to be on NI Labs) for on-chip debugging, which is the final step in the verification process. In terms of verification time there are aspects (like functional simulation) that are faster than traditional methods and others that are comparable, and still other that we are continuing to refine.
Ability to develop in the future - I am not sure what you mean here but we are certainly continuing to activiely develop on the RIO platform which includes FPGA as the key diffentiating technolgoy.  If you take a look at the NI Week keynote videos (ni.com/niweek) there is no doubt from both Day 1 and Day 2 that FPGA will be an important well maintained platform for many years to come.
2. Apologies for the statement in the document. The sentence should read that there are example for most board resources.
3. We do have plans to support a processor on the FPGA through LabVIEW FPGA. In fact, you will see technology on NI Labs soon that addresses this with MicroBlaze.
4. We do not currently have plans to support any other evaluation platforms. This support was created for our counterparts in the academic space to have a platform to learn the basics of digital design on a board that many schools already have in house. We are currently foccussing on rounding out more of our off-the-shelf platform with new PCI Express R Series boards, FlexRIO with new adapter modules, cRIO with new Virtex 5 backplanes, and more.
I hope this has anwered some of the questions you have.
Regards
Rick Kuhlman | LabVIEW FPGA Product Manager | National Instruments | ni.com/fpga
Check out the FPGA IPNet for browsing, downloading, and learning about LabVIEW FPGA IP Cores

64 bit LabVIEW FPGA 2009 driver for Xilinx SPARTAN 3E Starter Board

dear i need this module
we i install the module that i hava this appear to me
LabVIEW Support for Spartan-3E (incompatible with 64-bit platform)
is thier a version to supprt 64 bit???
best regards
hi ?Q>
Solved!
Go to Solution.

bad news
i will use Virtual machine to solve the problem
bet regads
hi ?Q>

How do I install Labview 64 bit support for the labview fpga module?

see subject.

Hi,
The LabVIEW FPGA Module uses the 32-bit version of the Xilinx tools, even on the 64-bit OS.
There is no 64 bit version of LabVIEW FPGA and you must have LabVIEW 32 bit
installed on your 64-bit machine to use the compatible version of
LabVIEW FPGA.
NI LabVIEW FPGA Module will run within the 32-bit emulation layer, Windows on Windows (WOW64).
regards,
Houssam Kassri
NI Germany

How can I install (download) a Labview FPGA code onto Altera FPGA chip using Labview FPGA module?

Hi there
Guys i'm a very new labview user (PhD student), my project is about ( design and implementation of a high speed-yet sophisticated system using Labview environment then install this project's code (using Labview FPGA module) onto Altera-made FPGA chip).
so kindly, can any body help me in this?...is there any way to connect labview with Altera FPGA?...please anything would be said 'd be of great benifits
thanks a lot in advance.

as previously mentioned, labview fpga only supports national instruments targets utilizing xilinx fpgas. the hdl generated by labview fpga is encrypted and cannot be used to synthesize a design outside the labview fpga design flow.
however, if you must use labview for your project, it might be possible for you to design the system in labview and use one of the labview embedded modules ( http://www.ni.com/embedded )to generate c code which you can then port to systemc and compile for the altera fpga. i'm not saying it will be easy, but it should be possible.

Labview FPGA for beginners.

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