Grrr... Xilinx compile failures

Question

I appreciate the effort NI has put into making FPGA programming available to the unwashed masses.  When things work correctly it's slicker than a greased seal in an oil factory.  When things go bad it's extremely frustrating with few clues about how to fix the problem.
I've been struggling with intermittent compile failures on a cRIO-9074.  The latest problem when I added code to make the fpga LED flash while the fpga is running.  That generated a compile error, so I removed that code.  Now it still won't compile, even though it's the exact same code as before.
I've attached the Xilinx log file.  There are several different types of errors, each of which is repeated multiple times.  Links are to the Xilinx KB articles:
ERROR:coreutil - ios failure
ERROR:sim:928 - Could not open destination 'PkgBeatleTypedefs.vhd' for writing.
ERROR:ConstraintSystem:58 - Constraint <INST "*oInputFalling*" TNM =
   "CcInputFallingRegs";> [toplevel_gen.ucf(141)]: INST "*oInputFalling*" does
   not match any design objects.
ERROR:ConstraintSystem:59 - Constraint <TIMESPEC "TS_AsynchMite30"= FROM
   PADS(mIoHWord_n) TO PADS(mIoDmaReq<*>) 0 ns;> [toplevel_gen.ucf(703)]: PADS
   "mIoHWord_n" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
According to Xilinx, the first error should be ignored--the design will load and run fine.  Is that possible when compiling within Labview?  Is there a way to run the compiler tools directly, and would that even help?  The second error requires modifying the UCF file, and the third requires various tools and options not available (afaik) to LV developers.
I've been fighting the FPGA compiler for about a month.  Its unpredicability is deadly for small businesses trying to deliver something to a customer.  I'm about ready to throw the whole thing in the trash and go in another direction, simply because I can more accurately estimate how long it will take me to implement on a different platform.
[Edit]
I just tried recompiling the fpga vi again.  This time I receive a new error:
LabVIEW FPGA:  An internal software error in the LabVIEW FPGA Module has occurred.  Please contact National Instruments technical support at ni.com/support.
Click the 'Details' button for additional information.
Compilation Time
Date submitted: 11/28/2012 9:28 AM
Last update: 11/28/2012 9:30 AM
Time waiting in queue: 00:05
Time compiling: 01:55
- PlanAhead: 01:50
- Core Generator: 00:00
- Synthesis - Xst: 00:01
- Translate: 00:01
Attachments:
XilinxLog.txt ‏1302 KB

Answer 1

I'm using a 9237 in slot 3 and setting the sample rate to 1.613 kS/sec.  Slots 1 and 2 have a 9411 and 9422 that I will read using the scan engine.  (Some of my RT test code uses the 9422, some doesn't.  It doesn't seem to be related to this problem.)
Interestingly, I added a small bit of code again to try and get the LED to flash while the FPGA is running.
...and I got all sorts of new compile errors, such as...
ERROR:HDLCompiler:806 -
   "C:/NIFPGA/jobs/Rtxj7d7_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" Line 208:
   Syntax error near "downto".
ERROR:HDLCompiler:806 -
   "C:/NIFPGA/jobs/Rtxj7d7_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" Line 224:
   Syntax error near "3".
ERROR:HDLCompiler:806 -
   "C:/NIFPGA/jobs/Rtxj7d7_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" Line 240:
   Syntax error near "}".
ERROR:HDLCompiler:806 -
   "C:/NIFPGA/jobs/Rtxj7d7_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" Line 244:
   Syntax error near "`".
At the very end of the log it says, "Sorry, too many errors.."  I guess it just gave up.  I know the feeling.
I tried deleting that code and recompiling the vi, and it still won't compile.  I assume if I create another new vi via copy and paste it will work again, but something weird is going on.
Attachments:
XilinxLog - FPGA Main 2 (DMA) - Added flashing LED.txt ‏141 KB