Xilinx Compilation Error: HDLCompiler:432 Formal eiosignal has no actual or default value

Hi,
I have compiled several programs for sbRIOs previously but have not run into compilation errors before. I can't seem to find any support to see what is actually going poorly. Any help with this would be appreciated!
The Compilation Status summary is as follows:
LabVIEW FPGA: The compilation failed due to a xilinx error.
Details:
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 87: Formal <eiosignal> has no actual or default value.
INFO:TclTasksC:1850 - process run : Synthesize - XST is done.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000032_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 106: Formal <eiosignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000033_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 125: Formal <eiosignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000034_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 144: Formal <eiosignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000035_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 163: Formal <eiosignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000036_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 182: Formal <eiosignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000037_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 201: Formal <eiosignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000038_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 220: Formal <eiosignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000039_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:854 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 50: Unit <vhdl_labview> ignored due to previous errors.
VHDL file C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd ignored due to errors
-->
Total memory usage is 189944 kilobytes
Number of errors : 9 ( 0 filtered)
Number of warnings : 4 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesize - XST" failed
Solved!
Go to Solution.

Hi DiracDeltaForce,
As a first pass, I would recommend disabling or deleting a section of code that you suspect may cause the compile error and see if you can get through synthesis. Once you get through a compile, you have at least isolated the trouble spot.
Something I would look for in your code is attempts to access the same IO node in multiple clock domains, ie inside and outside of SCTL (single-cycle timed loops), timed sequence structures, or in muliple timed structures with different clock rates. Attempting this would force LabVIEW to create arbitraion and hand-shaking logic to safely pass data between clock domains. This type of logic doesn't work in a timed structure because the hand-shaking operation takes multiple clock cycles.
If you are only using traditional sequence structures (rather than the timed sequence structures) I wouldn't suspect this type of issue.
-spex
Spex
National Instruments
To the pessimist, the glass is half empty; to the optimist, the glass is half full; to the engineer, the glass is twice as big as it needs to be...

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   2. The specified object is spelled correctly in the constraint source file.
According to Xilinx, the first error should be ignored--the design will load and run fine. Is that possible when compiling within Labview? Is there a way to run the compiler tools directly, and would that even help? The second error requires modifying the UCF file, and the third requires various tools and options not available (afaik) to LV developers.
I've been fighting the FPGA compiler for about a month. Its unpredicability is deadly for small businesses trying to deliver something to a customer. I'm about ready to throw the whole thing in the trash and go in another direction, simply because I can more accurately estimate how long it will take me to implement on a different platform.
[Edit]
I just tried recompiling the fpga vi again. This time I receive a new error:
LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support.
Click the 'Details' button for additional information.
Compilation Time
Date submitted: 11/28/2012 9:28 AM
Last update: 11/28/2012 9:30 AM
Time waiting in queue: 00:05
Time compiling: 01:55
- PlanAhead: 01:50
- Core Generator: 00:00
- Synthesis - Xst: 00:01
- Translate: 00:01
Attachments:
XilinxLog.txt ‏1302 KB

I'm using a 9237 in slot 3 and setting the sample rate to 1.613 kS/sec. Slots 1 and 2 have a 9411 and 9422 that I will read using the scan engine. (Some of my RT test code uses the 9422, some doesn't. It doesn't seem to be related to this problem.)
Interestingly, I added a small bit of code again to try and get the LED to flash while the FPGA is running.
...and I got all sorts of new compile errors, such as...
ERROR:HDLCompiler:806 -
   "C:/NIFPGA/jobs/Rtxj7d7_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" Line 208:
   Syntax error near "downto".
ERROR:HDLCompiler:806 -
   "C:/NIFPGA/jobs/Rtxj7d7_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" Line 224:
   Syntax error near "3".
ERROR:HDLCompiler:806 -
   "C:/NIFPGA/jobs/Rtxj7d7_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" Line 240:
   Syntax error near "}".
ERROR:HDLCompiler:806 -
   "C:/NIFPGA/jobs/Rtxj7d7_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" Line 244:
   Syntax error near "`".
At the very end of the log it says, "Sorry, too many errors.." I guess it just gave up. I know the feeling.
I tried deleting that code and recompiling the vi, and it still won't compile. I assume if I create another new vi via copy and paste it will work again, but something weird is going on.
Attachments:
XilinxLog - FPGA Main 2 (DMA) - Added flashing LED.txt ‏141 KB

HDL Compiler Error

Salve,
per la mia applicazione uso un crate PXIe (1062Q) con un RT-module 8102 ed una FlexRIO 7962R. Alla FlexRIO è connesso un AM custom. Nella mia applicazione genero un IP-core con il coregen di xilinx da importare come CLIP nel mio progetto (è una fifo dual clock con dimensione di bus dati differente tra scrittura e lettura). Premesso che con LV 2011 tutto funzionava correttamente, non appena ho installato LV 2012, e quindi, nella speranza di ottenere prestazioni ancora migliori, sono passato ad usare ISE 13.4, ho ri-generato IP-core della fifo (fifo generator 8.4 al posto del 7.2 della precedente versione), ho re-importato il codice nel mio progetto ma al momento di compilare il VI ho ricevuto il seguente errore (del quale allego anche il log xilinx):
English version:
Hi,
I'm using a PXIe crate(1062Q) with a RT-module 8102 and a FlexRIO 7962R. A custom AM is connected to the FlexRIO. I create a new IP-core with Xilinx coregen to import as CLIP in my project (the IP-CORE is a dual clock fifo with non-symmetric aspect ratios). Using LV 2011 all works fine, but with LV 2012 (ISE 13.4, fifo generator 8.4 instead of 7.2 of previous version), trying to have better performance, during compiling I received the following error (log xilinx as attached):
LabVIEW FPGA: The compilation failed due to a xilinx error.
Details:
ERROR:HDLCompiler:104 - "C:\NIFPGA\jobs\LejKY3B_DPeQegM\NiLvFpgaClipContainer.vhd" Line 149: Cannot find <fifo_generator_v8_4> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
ERROR:HDLCompiler:104 - "C:\NIFPGA\jobs\LejKY3B_DPeQegM\NiLvFpgaClipContainer.vhd" Line 162: Cannot find <fifo_generator_v8_4> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
ERROR:HDLCompiler:854 - "C:\NIFPGA\jobs\LejKY3B_DPeQegM\NiLvFpgaClipContainer.vhd" Line 95: Unit <clipcontainer_vhdl> ignored due to previous errors.
VHDL file C:\NIFPGA\jobs\LejKY3B_DPeQegM\NiLvFpgaClipContainer.vhd ignored due to errors
-->
Total memory usage is 203228 kilobytes
Number of errors   :    3 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    1 (   0 filtered)
Process "Synthesize - XST" failed
Grazie in anticipo a chiunque abbia una soluzione da proporre.
Thanks in advance to everyone have a solution to suggest.
Attachments:
XilinxLog.txt ‏133 KB

We had the same problem when switching to Ubuntu 14.04, and there actually is a solution for it: make sure your locales are set to English.
$> env | grep LC_*
should only show english (or C) locales, all others are known to cause parsing errors in some numbers, usually caused by wrong string-to-float conversions (e.g. 18,29 in german is 18.29 in english). You can change the locales in the file /etc/default/localesThis is not the first time we had problems with the locale settings, Xilinx does not seem to test their software with anything else than en_US, causing obscure bugs like this one.
HTH
Philipp

Error:HDLCompiler:104: Cannot find float_alg_pkg in library ieee_proposed

When I synthesize the VHDL code from Vivado HLS in Xilinx ISE, some errors appeared.
All the errors are caused by the ' aesl_fp_wrapper.vhd ' file and the first one is described like below:
ERROR:HDLCompiler:104:HDLCompiler:104 - "/home/xq32/code/rvc-cal/shared-cal-programs/meanShift/HLSBackend0801/HLSBackend/TopVHDL/aesl_fp_wrapper.vhd" Line 681: Cannot find <float_alg_pkg> in library <ieee_proposed>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
The code is like:
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.float_alg_pkg.all; (ERROR HAPPENED HERE)
entity AESL_WP_FLog is
generic (
    NUM_STAGE : INTEGER := 13;
    din0_WIDTH : INTEGER := 32;
    din1_WIDTH : INTEGER := 32;
    dout_WIDTH : INTEGER := 32);
port (
    clk, reset, ce : std_logic;
    din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
    din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
    dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FLog;
More information:
The Vivado HLS generate a folder: ieee_FP_pkg
The following files and folder are inside it:
aesl_fp_wrapper.vhd   fixed_pkg_c.vhd fuse.xmsgs
fixed_float_types_c.vhd float_pkg_c.vhd isim
Within the isim folder: isim>work>fixed_float_types.vdb
Does anyone have idea?
Many thanks

You should add a library which means <float_alg_pkg> .add to library

Xilinx Compilation Error: HDLCompiler:432 Formal eiosignal has no actual or default value

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